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ADS8405 Datasheet(PDF) 8 Page - Texas Instruments |
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ADS8405 Datasheet(HTML) 8 Page - Texas Instruments |
8 / 29 page www.ti.com ADS8405 SLAS427 – DECEMBER 2004 Terminal Functions NAME NO. I/O DESCRIPTION AGND 5, 8, 11, 12, 14, – Analog ground 15, 44, 45 BDGND 25, 35 – Digital ground for bus interface digital supply BUSY 36 O Status output. High when a conversion is in progress. BYTE 39 I Byte select input. Used for 8-bit bus reading. 0: No fold back 1: Low byte D[7:0] of the 16 most significant bits is folded back to high byte of the 16 most significant pins DB[15:8]. CONVST 40 I Convert start. The falling edge of this input ends the acquisition period and starts the hold period. CS 42 I Chip select. The falling edge of this input starts the acquisition period. 8-Bit Bus 16-Bit Bus Data Bus BYTE = 0 BYTE = 1 BYTE = 0 DB15 16 O D15 (MSB) D7 D15 (MSB) DB14 17 O D14 D6 D14 DB13 18 O D13 D5 D13 DB12 19 O D12 D4 D12 DB11 20 O D11 D3 D11 DB10 21 O D10 D2 D10 DB9 22 O D9 D1 D9 DB8 23 O D8 D0 (LSB) D8 DB7 26 O D7 All ones D7 DB6 27 O D6 All ones D6 DB5 28 O D5 All ones D5 DB4 29 O D4 All ones D4 DB3 30 O D3 All ones D3 DB2 31 O D2 All ones D2 DB1 32 O D1 All ones D1 DB0 33 O D0 (LSB) All ones D0 (LSB) –IN 7 I Inverting input channel +IN 6 I Noninverting input channel NC 3 – No connection REFIN 1 I Reference input REFM 47, 48 I Reference ground REFOUT 2 O Reference output. Add 1-µF capacitor between the REFOUT pin and REFM pin when the internal reference is used. RESET 38 I Current conversion is aborted and output latches are cleared (set to zeros) when this pin is asserted low. RESET works independantly of CS. RD 41 I Synchronization pulse for the parallel output. When CS is low, this serves as the output enable and puts the previous conversion result on the bus. +VA 4, 9, 10, 13, 43, – Analog power supplies, 5-V dc 46 +VBD 24, 34, 37 – Digital power supply for bus 8 |
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