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MMUN2130L Datasheet(PDF) 1 Page - ON Semiconductor

Part # MMUN2130L
Description  Digital Transistors (BRT) R1 = 1 k, R2 = 1 k
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

MMUN2130L Datasheet(HTML) 1 Page - ON Semiconductor

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© Semiconductor Components Industries, LLC, 2013
February, 2013 − Rev. 2
1
Publication Order Number:
DTA113E/D
MUN2130, MMUN2130L,
MUN5130, DTA113EE,
DTA113EM3, NSBA113EF3
Digital Transistors (BRT)
R1 = 1 kW, R2 = 1 kW
PNP Transistors with Monolithic Bias
Resistor Network
This series of digital transistors is designed to replace a single
device and its external resistor bias network. The Bias Resistor
Transistor (BRT) contains a single transistor with a monolithic bias
network consisting of two resistors; a series base resistor and a base−
emitter resistor. The BRT eliminates these individual components by
integrating them into a single device. The use of a BRT can reduce
both system cost and board space.
Features
Simplifies Circuit Design
Reduces Board Space
Reduces Component Count
S and NSV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC-Q101 Qualified
and PPAP Capable
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
MAXIMUM RATINGS (TA = 25°C)
Rating
Symbol
Max
Unit
Collector−Base Voltage
VCBO
50
Vdc
Collector−Emitter Voltage
VCEO
50
Vdc
Collector Current − Continuous
IC
100
mAdc
Input Forward Voltage
VIN(fwd)
10
Vdc
Input Reverse Voltage
VIN(rev)
10
Vdc
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
PIN 3
COLLECTOR
(OUTPUT)
PIN 2
EMITTER
(GROUND)
PIN 1
BASE
(INPUT)
R1
R2
See detailed ordering, marking, and shipping information in
the package dimensions section on page 2 of this data sheet.
ORDERING INFORMATION
http://onsemi.com
PIN CONNECTIONS
SC−75
CASE 463
STYLE 1
MARKING DIAGRAMS
XXX
= Specific Device Code
M
= Date Code*
G
=Pb−Free Package
(Note: Microdot may be in either location)
*Date Code orientation may vary depending
upon manufacturing location.
SC−59
CASE 318D
STYLE 1
SOT−23
CASE 318
STYLE 6
SC−70/SOT−323
CASE 419
STYLE 3
SOT−723
CASE 631AA
STYLE 1
SOT−1123
CASE 524AA
STYLE 1
XX MG
G
1
1
XXX MG
G
XX MG
G
1
XX M
1
X M
XX M
1
1


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