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Z8523020VSG Datasheet(PDF) 10 Page - Zilog, Inc. |
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Z8523020VSG Datasheet(HTML) 10 Page - Zilog, Inc. |
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10 / 118 page  PS005308-0609 Pin Descriptions Z80230/Z85230/L Product Specification 5 When used as DMA Request line (WR14 bit 2 is 1), the timing for the deactivation request can be programmed in Write Register 7’ (WR7’) bit 4. If this bit is 1, the DTR/REQ pin is deactivated with the same timing as the W/REQ pin. If 0, the deactivation timing of DTR/ REQ pin is four clock cycles, the same as in the Z80C30/Z85C30. W/REQA, W/REQB (Wait/request (Output, Open-drain When Programmed For WAIT Function, Driven High And Low When Programmed For Request Function))— These dual-purpose outputs may be programmed as REQUEST lines for a DMA controller or as WAIT lines to synchronize the CPU to the ESCC data rate. The reset state is WAIT. RxDA, RxDB (Receive Data (inputs, active High))— These inputs receive serial data at standard Transistor-Transistor Logic (TTL) levels. RTxCA, RTxCB (Receive/Transmit Clocks (Input, Active Low))— These pins can be programmed to several modes of operation. In each channel, RTxC may supply the fol- lowing: • Receive clock and/or the transmit clock • Clock for the baud rate generator (BRG) • Clock for the Digital Phase-Locked Loop These pins can also be programmed for use with the respective SYNC pins as a crystal oscillator. The receive clock may be 1, 16, 32, or 64 times the data rate in ASYNCHRO- NOUS modes. TxDA, TxDB (Transmit Data (Output, Active High))— These output transmit serial data at standard TTL levels. TRxCA, TRxCB (Transmit/Receive Clocks (Input or Output, Active Low))— These pins can be programmed in several different modes. When configured as an input, the TRxC may supply the receive clock and/or the transmit clock. When configured as an out- put, TRxC can echo the clock output of the Digital Phase-Locked Loop, the crystal oscilla- tor, the BRG or the transmit clock. PCLK (Clock (Input))— This clock is the master ESCC clock used to synchronize internal signals. PCLK is a TTL level signal. PCLK is not required to have any phase relationship with the master system clock. IEI (Interrupt Enable In (Input, Active High))— IEI is used with IEO to form an interrupt daisy chain when there is more than one interrupt-driven device. A High IEI indicates that no higher priority device has an Interrupt Under Service (IUS) or is requesting an interrupt. IEO (Interrupt Enable Out (Output, Active High))— IEO is High only if IEI is High and the CPU is not servicing an ESCC interrupt. During an Interrupt Acknowledge Cycle, IEO is also driven Low if the ESCC is requesting an interrupt. IEO can be connected to the next lower priority device’s IEI input, and in this case inhibits interrupts from lower prior- ity devices. |
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