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Z8927320VSG Datasheet(PDF) 4 Page - Zilog, Inc. |
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Z8927320VSG Datasheet(HTML) 4 Page - Zilog, Inc. |
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4 / 60 page  Z89223/273/323/373 16-Bit Digital Signal Processors with A/D Converter ZiLOG 4 DS000202-DSP0599 PIN FUNCTIONS EA2–EA0. External Address Bus (output, latched). These pins provide the External Register Address. This address bus is driven during both internal and external accesses. One of up to seven user-defined external registers is selected by the processor for reads or writes. EXT7 is always reserved for use by the processor. ED15–ED0. External Data Bus (input/output). These pins are the data bus for the user-defined external registers, and are shared by Port0. These pins are normally tristated, ex- cept when these registers are specified as destination reg- isters in a write instruction to an external peripheral, or when Port0 is enabled for output. This bus uses the control signals RD/WR, DS, and WAIT, and address pins EA2–EA0. DS . Data Strobe (output). This pin provides the data strobe signal for the ED Bus. DS is active for transfers to/from ex- ternal peripherals only. RD/WR. Read/Write Select (output). This pin controls the data direction signal for the External Data Bus. Data is avail- able from the processor on ED15–ED0 when this signal and DS are both Low. WAIT . Wait State (input). This pin is sampled at the rising edge of the clock with appropriate setup and hold times. A single wait-state can be generated internally by setting the appropriate bits in the wait state register. The user must drive this line if multiple wait states are required. This pin is shared with Port2. CLKI. Clock (input). This pin is the clock circuit input. It can be driven by a signal or connected to a 32 KHz crystal. CLKO. Clock (output). This pin is the clock circuit output. It is used for operation with a 32 KHz crystal and the PLL to generate the system clock. HALT . Halt State (input). This pin stops program execution. The processor continuously executes NOPs and the pro- gram counter remains constant while this pin is held Low. This pin offers an internal pull-up. RESET . Reset (input). This pin resets the processor. It push- es the contents of the Program Counter (PC) onto the stack and then fetches a new PC value from program memory ad- dress 0FFCH after the RESET signal is released. The Status register is set to all zeros. At power-up RAM and other reg- isters are undefined, however, they are left unchanged with subsequent resets. RESET can be asserted asynchronously. AN0–AN3. Analog Inputs (input). These are the analog in- put pins. The analog input signal should be between VALO and VAHI for accurate conversions. VAHI. Analog High Reference Voltage (input). This pin provides the reference for the full scale voltage of the analog input signals. VALO. Analog Low Reference Voltage (input). This pin provides the reference for the zero voltage of the analog in- put signals. AVCC–AGND. Filtered Analog Power and Ground must be provided on separate pins to reduce digital noise in the an- alog circuits. Multifunction Pins. The Z89223/273/323/373 DSP fami- ly offers a user-configurable I/O structure, which means that most of the I/O pins offer dual functions. The function, direction (input or output), and for output, the characteris- tics (push-pull or open drain) are all under user-control, by programming the configuration registers appropriately as described in the I/O Ports section. The following share I/O Port pins: INT0–INT2. External Interrupts (input, edge-triggered). These pins provide three of the eight interrupt sources to the Interrupt Controller. Each is programmable to be rising- edge or falling-edge triggered. The other five interrupt sources are from the on-chip peripherals. CLKOUT. System Clock (output). This pin provides access to the internal processor clock. SDI. Serial Data In (input). This pin is the SPI serial data input. SDO. Serial Data Out (output). This pin is the SPI serial data output. SS. Slave Select (input). This pin is used in SPI Slave Mode only. SS advises the SPI that it is the target of a serial transfer from an external Master. SCLK. SPI Clock (output/input). This pin is an output in Master mode and an input in Slave mode. UI0, UI1. User inputs (input). These general-purpose input pins are directly tested by the conditional branch instruc- tions. They can also be read as bits in the status register. These are asynchronous input signals that require no special clock synchronization. Counter/Timer0 and Counter/Timer1 may use either of these pins as input. UI2. User Input (input). This pin is the input to Counter/Timer 2. TMO0/UO0. Counter/Timer Output or User Output 0 (out- put). Counter/Timer 0 and Counter/Timer 1 can be pro- grammed to provide output on this pin. When User Outputs are enabled, and the Counter/Timer is disabled, this pin pro- vides the complement of Status Register bit 5. |
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