Technical Note

11/21

BR24T□□□□Series

www.rohm.com

2011.03 - Rev.A

© 2011 ROHM Co., Ltd. All rights reserved.

●Read Command

○Read cycle

Data of EEPROM is read. In read cycle, there are random read cycle and current read cycle. Random read cycle is a

command to read data by designating address, and is used generally. Current read cycle is a command to read data of

internal address register without designating address, and is used when to verify just after write cycle. In both the read

cycles, sequential read cycle is available, and the next address data can be read in succession.

・In random read cycle, data of designated word address can be read.

・When the command just before current read cycle is random read cycle, current read cycle (each including sequential

read cycle), data of incremented last read address (n)-th address, i.e., data of the (n+1)-th address is output.

・When ACK signal 'LOW' after D0 is detected, and stop condition is not sent from master (µ-COM) side, the next

address data can be read in succession.

・Read cycle is ended by stop condition where 'H' is input to ACK signal after D0 and SDA signal is started at SCL

signal 'H' .

・When 'H' is not input to ACK signal after D0, sequential read gets in, and the next data is output.

Therefore, read command cycle cannot be ended. When to end read command cycle, be sure input stop condition to

input 'H' to ACK signal after D0, and to start SDA at SCL signal 'H'.

・Sequential read is ended by stop condition where 'H' is input to ACK signal after arbitrary D0 and SDA is started at SCL

signal 'H'.

Fig.43 Random read cycle (BR24T01/02/04/08/16-W)

Fig.44 Random read cycle (BR24T32/64/128/256/512/1M-W)

*1 As for WA12, BR24T32-W become Don’t care.

As for WA13, BR24T32/64-W become Don’t care.

As for WA14, BR24T32/64/128-W become Don’t care.

As for WA15, BR24T32/64/128/256-W become Don’t care.

Fig.45 Current read cycle

Fig.46 Sequential read cycle (in the case of current read cycle)

*1

In BR24T16-W, A2 becomes P2.

*2

In BR24T08/16-W, A1 becomes P1.

*3

In BR24T08/16/1M-W, A0 becomes P0.

Note)

*1

As for WA7,BR24T01-W become Don’t care.

Fig.47 Difference of slave address of each type

A2

A0

A1

A1

A2

W

R

I

T

E

S

T

A

R

T

R

/

W

A

C

K

S

T

O

P

1st WORD

ADDRESS

（）

SDA

LINE

A

C

K

A

C

K

DATA(n)

A

C

K

SLAVE

ADDRESS

1 0

0

1

A0

D7

D0

2nd WORD

ADDRESS(n)

A

C

K

S

T

A

R

T

SLAVE

ADDRESS

1 0

0

1

R

/

W

R

E

A

D

WA

0

Note)

*1

WA

15

WA

14

WA

13

WA

12

WA

11

W

R

I

T

E

S

T

A

R

T

R

/

W

A

C

K

S

T

O

P

WORD

ADDRESS(n)

SDA

LINE

A

C

K

A

C

K

DATA(n)

A

C

K

SLAVE

ADDRESS

10

0

1

A0

A1

A2

WA

7

A0

D0

SLAVE

ADDRESS

10

0

1A1

A2

S

T

A

R

T

D7

R

/

W

R

E

A

D

WA

0

Note)

*1

S

T

A

R

T

S

T

O

P

SDA

LINE

A

C

K

DATA(n)

A

C

K

SLAVE

ADDRESS

10

0

1

A0

A1

A2

D0

D7

R

/

W

R

E

A

D

Note)

R

E

A

D

S

T

A

R

T

R

/

W

A

C

K

S

T

O

P

DATA(n)

SDA

LINE

A

C

K

A

C

K

DATA(n+x)

A

C

K

SLAVE

ADDRESS

10

0

1

A0

A1

A2

D0

D7

D0

D7

Note）

*1

As for WA12, BR24T32-W becomes Don't care.

As for WA13, BR24T32/64-W becomes Don't care.

As for WA14, BR24T32/64/128-W becomes Don't care.

As for WA15, BR24T32/64/128/256-W becomes Don't care.

*2

As for BR24T128/256-W becomes (n+63)

As for BR24T512-W becomes (n+127)

As for BR24T1M-W becomes (n+255)

*1

As for WA7, BR24T01-W becomes Don't care.

*2

As for BR24T01/02-W becomes (n+7)

1

0

0

1A0

A1

A2

*1 *2 *3