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C8051F040-GQR Datasheet(PDF) 58 Page - Silicon Laboratories

Part No. C8051F040-GQR
Description  Mixed Signal ISP Flash MCU Family
Download  328 Pages
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Manufacturer  SILABS [Silicon Laboratories]
Direct Link  http://www.silabs.com
Logo SILABS - Silicon Laboratories

C8051F040-GQR Datasheet(HTML) 58 Page - Silicon Laboratories

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C8051F040/1/2/3/4/5/6/7
58
Rev. 1.5
SFR Definition 5.5. ADC0CF: ADC0 Configuration Register
Bits7-3:
AD0SC4-0: ADC0 SAR Conversion Clock Period Bits
SAR Conversion clock is derived from system clock by the following equation, where
AD0SC refers to the 5-bit value held in AD0SC4-0, and CLKSAR0 refers to the desired ADC0
SAR clock. See Table 5.2 for SAR clock configuration requirements.
*
or
*Note: AD0SC is the rounded-up result.
Bits2-0:
AMP0GN2-0: ADC0 Internal Amplifier Gain (PGA)
000: Gain = 1
001: Gain = 2
010: Gain = 4
011: Gain = 8
10x: Gain = 16
11x: Gain = 0.5
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
AD0SC4
AD0SC3
AD0SC2
AD0SC1
AD0SC0 AMP0GN2 AMP0GN1 AMP0GN0 11111000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
SFR Page:
0xBC
0
AD0SC
SYSCLK
CLK
SAR0
-----------------------
1
–
CLK
SAR0
SYSCLK
AD0SC
1
+
----------------------------
=


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