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C8051F040-GQR Datasheet(PDF) 69 Page - Silicon Laboratories

Part # C8051F040-GQR
Description  Mixed Signal ISP Flash MCU Family
Download  328 Pages
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Manufacturer  SILABS [Silicon Laboratories]
Direct Link  http://www.silabs.com
Logo SILABS - Silicon Laboratories

C8051F040-GQR Datasheet(HTML) 69 Page - Silicon Laboratories

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C8051F040/1/2/3/4/5/6/7
Rev. 1.5
69
6.
10-Bit ADC (ADC0, C8051F042/3/4/5/6/7 Only)
The ADC0 subsystem for the C8051F042/3/4/5/6/7 consists of a 9-channel, configurable analog multi-
plexer (AMUX0), a programmable gain amplifier (PGA0), and a 100 ksps, 10-bit successive-approxima-
tion-register ADC with integrated track-and-hold and Programmable Window Detector (see block diagram
in Figure 6.1). The AMUX0, PGA0, Data Conversion Modes, and Window Detector are all configurable
under software control via the Special Function Registers shown in Figure 6.1. The voltage reference used
by ADC0 is selected as described in Section “9. Voltage Reference (C8051F040/2/4/6)” on page 113 for
C8051F042/4/6 devices, or Section “10. Voltage Reference (C8051F041/3/5/7)” on page 117 for
C8051F043/5/7 devices. The ADC0 subsystem (ADC0, track-and-hold and PGA0) is enabled only when
the AD0EN bit in the ADC0 Control register (ADC0CN) is set to logic 1. The ADC0 subsystem is in low
power shutdown when this bit is logic 0.
Figure 6.1. 10-Bit ADC0 Functional Block Diagram
6.1.
Analog Multiplexer and PGA
The analog multiplexer can input analog signals to the ADC from four external analog input pins, Port 3
port pins (optionally configured as analog input pins), High Voltage Difference Amplifier, and an internally
connected on-chip temperature sensor (temperature transfer function is shown in Figure 6.6). AMUX input
pairs can be programmed to operate in either differential or single-ended mode. This allows the user to
select the best measurement technique for each input channel, and even accommodates mode changes
"on-the-fly". The AMUX defaults to all single-ended inputs upon reset. There are three registers associated
with the AMUX: the Channel Selection register AMX0SL (SFR Definition 6.2), the Configuration register
AMX0CF (SFR Definition 6.1), and the Port Pin Selection register AMX0PRT (SFR Definition 6.3).
Table 6.1 shows AMUX functionality by channel for each possible configuration. The PGA amplifies the
AMUX output signal by an amount determined by the states of the AMP0GN2-0 bits in the ADC0 Configu-
ration register, ADC0CF (SFR Definition 6.5). The PGA can be software-programmed for gains of 0.5, 2, 4,
8 or 16. Gain defaults to unity on reset.
10-Bit
SAR
ADC
+
-
AV+
TEMP
SENSOR
10
9-to-1
AMUX
(SE or
DIFF)
AV+
20
10
AD0EN
X
Start Conversion
AGND
AMX0CF
ADC0LTL
ADC0LTH
ADC0GTL
ADC0GTH
AMX0SL
ADC0CF
ADC0CN
Timer 3 Overflow
00
01
10
11
AD0BUSY (W)
CNVSTR0
AD0WINT
Comb.
Logic
HV
Input
Port 3
I/O Pins
Analog
Input
Pins
AGND
Timer 2 Overflow


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