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C8051F040-GQR Datasheet(PDF) 71 Page - Silicon Laboratories |
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C8051F040-GQR Datasheet(HTML) 71 Page - Silicon Laboratories |
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71 / 328 page  C8051F040/1/2/3/4/5/6/7 Rev. 1.5 71 SFR Definition 6.1. AMX0CF: AMUX0 Configuration SFR Definition 6.2. AMX0SL: AMUX0 Channel Select Bits7-4: UNUSED. Read = 0000b; Write = don’t care Bit3: PORT3IC: Port 3 even/odd Pin Input Pair Configuration Bit 0: Port 3 even and odd input channels are independent single-ended inputs 1: Port 3 even and odd input channels are (respectively) +, - differential input pair Bit2: HVDA2C: HVDA 2’s Compliment Bit 0: HVDA output measured as an independent single-ended input 1: 2’s compliment value Result from HVDA Bit1: AIN23IC: AIN2, AIN3 Input Pair Configuration Bit 0: AIN2 and AIN3 are independent single-ended inputs 1: AIN2, AIN3 are (respectively) +, - differential input pair Bit0: AIN01IC: AIN0, AIN1 Input Pair Configuration Bit 0: AIN0 and AIN1 are independent single-ended inputs 1: AIN0, AIN1 are (respectively) +, - differential input pair NOTE: The ADC0 Data Word is in 2’s complement format for channels configured as differential. R R R R R/W R/W R/W R/W Reset Value - - - - PORT3IC HVDA2C AIN23IC AIN01IC 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: SFR Address: SFR Page: 0xBA 0 Bits7-4: UNUSED. Read = 0000b; Write = don’t care Bits3-0: AMX0AD3-0: AMX0 Address Bits 0000-1111b: ADC Inputs selected per Table 6.1. R R R R R/W R/W R/W R/W Reset Value - - - - AMX0AD3 AMX0AD2 AMX0AD1 AMX0AD0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: SFR Page: 0xBB 0 |
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