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C8051F040-GQR Datasheet(PDF) 76 Page - Silicon Laboratories |
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C8051F040-GQR Datasheet(HTML) 76 Page - Silicon Laboratories |
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76 / 328 page  C8051F040/1/2/3/4/5/6/7 76 Rev. 1.5 6.3. ADC Modes of Operation ADC0 has a maximum conversion speed of 100 ksps. The ADC0 conversion clock is derived from the sys- tem clock divided by the value held in the ADC0SC bits of register ADC0CF. 6.3.1. Starting a Conversion A conversion can be initiated in one of four ways, depending on the programmed states of the ADC0 Start of Conversion Mode bits (AD0CM1, AD0CM0) in ADC0CN. Conversions may be initiated by the following: • Writing a ‘1’ to the AD0BUSY bit of ADC0CN; • A Timer 3 overflow (i.e., timed continuous conversions); • A rising edge detected on the external ADC convert start signal, CNVSTR0; • A Timer 2 overflow (i.e., timed continuous conversions). The AD0BUSY bit is set to logic 1 during conversion and restored to logic 0 when conversion is complete. The falling edge of AD0BUSY triggers an interrupt (when enabled) and sets the AD0INT interrupt flag (ADC0CN.5). Converted data is available in the ADC0 data word MSB and LSB registers, ADC0H, ADC0L. Converted data can be either left or right justified in the ADC0H:ADC0L register pair (see example in Figure 6.7) depending on the programmed state of the AD0LJST bit in the ADC0CN register. When initiating conversions by writing a ‘1’ to AD0BUSY, the AD0INT bit should be polled to determine when a conversion has completed (ADC0 interrupts may also be used). The recommended polling proce- dure is shown below. Step 1. Write a ‘0’ to AD0INT; Step 2. Write a ‘1’ to AD0BUSY; Step 3. Poll AD0INT for ‘1’; Step 4. Process ADC0 data. 6.3.2. Tracking Modes According to Table 6.2, each ADC0 conversion must be preceded by a minimum tracking time for the con- verted result to be accurate. The AD0TM bit in register ADC0CN controls the ADC0 track-and-hold mode. In its default state, the ADC0 input is continuously tracked when a conversion is not in progress. When the AD0TM bit is logic 1, ADC0 operates in low-power tracking mode. In this mode, each conversion is pre- ceded by a tracking period of 3 SAR clocks after the start-of-conversion signal. When the CNVSTR0 signal is used to initiate conversions in low-power tracking mode, ADC0 tracks only when CNVSTR0 is low; con- version begins on the rising edge of CNVSTR0 (see Figure 6.4). Tracking can also be disabled when the entire chip is in low power standby or sleep modes. Low-power tracking mode is also useful when AMUX or PGA settings are frequently changed, to ensure that settling time requirements are met (see Section “6.3.3. Settling Time Requirements” on page 78). |
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