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C8051F040-GQR Datasheet(PDF) 92 Page - Silicon Laboratories

Part # C8051F040-GQR
Description  Mixed Signal ISP Flash MCU Family
Download  328 Pages
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Manufacturer  SILABS [Silicon Laboratories]
Direct Link  http://www.silabs.com
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C8051F040-GQR Datasheet(HTML) 92 Page - Silicon Laboratories

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C8051F040/1/2/3/4/5/6/7
92
Rev. 1.5
7.2.
ADC2 Modes of Operation
ADC2 has a maximum conversion speed of 500 ksps. The ADC2 conversion clock (SAR2 clock) is a
divided version of the system clock, determined by the AD2SC bits in the ADC2CF register (system clock
divided by (AD2SC + 1) for 0
 AD2SC 31). The maximum ADC2 conversion clock is 7.5 MHz.
7.2.1. Starting a Conversion
A conversion can be initiated in one of five ways, depending on the programmed states of the ADC2 Start
of Conversion Mode bits (AD2CM2–0) in ADC2CN. Conversions may be initiated by the following:
•Writing a ‘1’ to the AD2BUSY bit of ADC2CN;
•A Timer 3 overflow (i.e., timed continuous conversions);
•A rising edge detected on the external ADC convert start signal, CNVSTR2 or CNVSTR0 (see
important note below);
•A Timer 2 overflow (i.e., timed continuous conversions);
•Writing a ‘1’ to the AD0BUSY of register ADC0CN (initiate conversion of ADC2 and ADC0 with a
single software command).
An important note about external convert start (CNVSTR0 and CNVSTR2): If CNVSTR2 is enabled in the
digital crossbar (Section “17.1. Ports 0 through 3 and the Priority Crossbar Decoder” on page 204),
CNVSTR2 will be the external convert start signal for ADC2. However, if only CNVSTR0 is enabled in the
digital crossbar and CNVSTR2 is not enabled, then CNVSTR0 may serve as the start of conversion for
both ADC0 and ADC2. This permits synchronous sampling of both ADC0 and ADC2.
During conversion, the AD2BUSY bit is set to logic 1 and restored to 0 when conversion is complete. The
falling edge of AD2BUSY triggers an interrupt (when enabled) and sets the interrupt flag in ADC2CN. Con-
verted data is available in the ADC2 data word, ADC2.
When a conversion is initiated by writing a ‘1’ to AD2BUSY, it is recommended to poll AD2INT to determine
when the conversion is complete. The recommended procedure is:
Step 1. Write a ‘0’ to AD2INT;
Step 2. Write a ‘1’ to AD2BUSY;
Step 3. Poll AD2INT for ‘1’;
Step 4. Process ADC2 data.
7.2.2. Tracking Modes
According to Table 7.2, each ADC2 conversion must be preceded by a minimum tracking time for the con-
verted result to be accurate. The AD2TM bit in register ADC2CN controls the ADC2 track-and-hold mode.
In its default state, the ADC2 input is continuously tracked, except when a conversion is in progress. When
the AD2TM bit is logic 1, ADC2 operates in low-power tracking mode. In this mode, each conversion is pre-
ceded by a tracking period of 3 SAR clocks (after the start-of-conversion signal). When the CNVSTR2 (or
CNVSTR0, See Section 7.2.1 above) signal is used to initiate conversions in low-power tracking mode,
ADC2 tracks only when CNVSTR2 is low; conversion begins on the rising edge of CNVSTR2 (see
Figure 7.2). Tracking can also be disabled (shutdown) when the entire chip is in low power standby or
sleep modes. Low-power Track-and-Hold mode is also useful when AMUX or PGA settings are frequently
changed, due to the settling time requirements described in Section “7.2.3. Settling Time Require-
ments” on page 94.


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