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C8051F040-GQR Datasheet(PDF) 21 Page - Silicon Laboratories

Part # C8051F040-GQR
Description  Mixed Signal ISP Flash MCU Family
Download  328 Pages
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Manufacturer  SILABS [Silicon Laboratories]
Direct Link  http://www.silabs.com
Logo SILABS - Silicon Laboratories

C8051F040-GQR Datasheet(HTML) 21 Page - Silicon Laboratories

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C8051F040/1/2/3/4/5/6/7
Rev. 1.5
21
Figure 1.1. C8051F040/2 Block Diagram
UART1
SMBus
SPI Bus
PCA
Timers
0,1,2,3,4
VDD
VDD
VDD
DGND
DGND
DGND
/RST
XTAL1
XTAL2
P2.0
P2.7
P0.0
P0.7
DAC1
DAC1
(12-Bit)
VREF
DAC0
(12-Bit)
AIN0.0
DAC0
VREF
UART0
8:1
MONEN
WDT
VREFD
VREF0
P7 Latch
P5 Latch
P6 Latch
P5.0/A8
P5.7/A51
P5
DRV
P6.0/A0
P6.7/A7
P6
DRV
P4
DRV
P4.5/ALE
P4.6/RD
P4.7/WR
P4.4
Addr [7:0]
Addr [15:8]
Ctrl Latch
Data Latch
A
M
U
X
8:2
HVAIN+
HVAIN-
HVREF
HVCAP
HVAMP
TEMP
SENSOR
P0
Drv
P1
Drv
P2
Drv
P3
Drv
Port
0,1,2,3
&4
Latches
CAN
2.0B
CANTX
8
0
5
1
C
o
r
e
Reset
A
M
U
X
Prog
Gain
ADC
100 ksps
(12 or 10-
Bit)
32x136
CANRAM
256 byte
RAM
4 kB
RAM
P3.0
P3.7
P1.0
P1.7
64 kB
Flash
System
Clock
Internal
Oscillator
External
Oscillator
Circuit
VDD
Monitor
C
R
O
S
S
B
A
R
Data [7:0]
Address [15:0]
Bus Control
Digital Power
Memories
Port 4 <from crossbar>
A
M
U
X
Prog
Gain
ADC
500 ksps
(8-Bit)
VREF2
P4.0
SFR Bus
P7
DRV
P7.0/D0
P7.7/D7
AV+
Debug HW
Boundary Scan
JTAG
Logic
TCK
TMS
TDI
TDO
AGND
AGND
AGND
AV+
AV+
Analog Power
P2.7
P2.6
+
-
CP0
P2.3
P2.2
+
-
CP1
P2.5
P2.4
+
-
CP2
AIN0.3
AIN0.2
AIN0.1
CANRX
External Memory Data
Bus


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