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C8051F040-GQR Datasheet(PDF) 29 Page - Silicon Laboratories

Part # C8051F040-GQR
Description  Mixed Signal ISP Flash MCU Family
Download  328 Pages
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Manufacturer  SILABS [Silicon Laboratories]
Direct Link  http://www.silabs.com
Logo SILABS - Silicon Laboratories

C8051F040-GQR Datasheet(HTML) 29 Page - Silicon Laboratories

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C8051F040/1/2/3/4/5/6/7
Rev. 1.5
29
1.4.
Programmable Digital I/O and Crossbar
The standard 8051 Ports (0, 1, 2, and 3) are available on the MCUs. The C8051F040/2/4/6 have 4 addi-
tional 8-bit ports (4, 5, 6, and 7) for a total of 64 general-purpose I/O Ports. The Ports behave like the stan-
dard 8051 with a few enhancements.
Each port pin can be configured as either a push-pull or open-drain output. Also, the "weak pullups" which
are normally fixed on an 8051 can be globally disabled, providing additional power saving capabilities for
low-power applications.
Perhaps the most unique enhancement is the Digital Crossbar. This is essentially a large digital switching
network that allows mapping of internal digital system resources to Port I/O pins on P0, P1, P2, and P3
(See Figure 1.9). Unlike microcontrollers with standard multiplexed digital I/O ports, all combinations of
functions are supported with all package options offered.
The on-chip counter/timers, serial buses, HW interrupts, ADC Start of Conversion input, comparator out-
puts, and other digital signals in the controller can be configured to appear on the Port I/O pins specified in
the Crossbar Control registers. This allows the user to select the exact mix of general purpose Port I/O and
digital resources needed for the particular application.
Figure 1.9. Digital Crossbar Diagram
External
Pins
Digital
Crossbar
Priority
Decoder
SMBus
2
SPI
4
UART0
2
PCA
2
T0, T1,
T2, T2EX,
T3, T3EX,
T4,T4EX,
/INT0,
/INT1
P1.0
P1.7
P2.0
P2.7
P0.0
P0.7
Highest
Priority
Lowest
Priority
8
8
Comptr.
Outputs
Highest
Priority
Lowest
Priority
UART1
6
2
P3.0
P3.7
8
8
P0MDOUT, P1MDOUT,
P2MDOUT, P3MDOUT
Registers
XBR0, XBR1, XBR2,
XBR3 P1MDIN,
P2MDIN, P3MDIN
Registers
P1
I/O
Cells
P3
I/O
Cells
P0
I/O
Cells
P2
I/O
Cells
8
Port
Latches
P0
P1
P2
8
8
8
P3
8
(P2.0-P2.7)
(P1.0-P1.7)
(P0.0-P0.7)
(P3.0-P3.7)
To
ADC2
Input
To External
Memory
Interface
(EMIF)
To
ADC0
Input
To
Comparators
/SYSCLK
CNVSTR0
CNVSTR2


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