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C8051F040-GQR Datasheet(PDF) 37 Page - Silicon Laboratories |
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C8051F040-GQR Datasheet(HTML) 37 Page - Silicon Laboratories |
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37 / 328 page  C8051F040/1/2/3/4/5/6/7 Rev. 1.5 37 4. Pinout and Package Definitions Table 4.1. Pin Definitions Name Pin Numbers Type Description F040/2/4/6 F041/3/5/7 VDD 37, 64, 90 24, 41, 57 Digital Supply Voltage. Must be tied to +2.7 to +3.6 V. DGND 38, 63, 89 25, 40, 56 Digital Ground. Must be tied to Ground. AV+ 8, 11, 14 3, 6 Analog Supply Voltage. Must be tied to +2.7 to +3.6 V. AGND 9, 10, 13 4, 5 Analog Ground. Must be tied to Ground. TMS 1 58 D In JTAG Test Mode Select with internal pullup. TCK 2 59 D In JTAG Test Clock with internal pullup. TDI 3 60 D In JTAG Test Data Input with internal pullup. TDI is latched on the rising edge of TCK. TDO 4 61 D Out JTAG Test Data Output with internal pullup. Data is shifted out on TDO on the falling edge of TCK. TDO out- put is a tri-state driver. /RST 5 62 D I/O Device Reset. Open-drain output of internal VDD monitor. Is driven low when VDD is < 2.7 V and MONEN is high. An external source can initiate a system reset by driving this pin low. XTAL1 26 17 A In Crystal Input. This pin is the return for the internal oscilla- tor circuit for a crystal or ceramic resonator. For a preci- sion internal clock, connect a crystal or ceramic resonator from XTAL1 to XTAL2. If overdriven by an external CMOS clock, this becomes the system clock. XTAL2 27 18 A Out Crystal Output. This pin is the excitation driver for a crystal or ceramic resonator. MONEN 28 19 D In VDD Monitor Enable. When tied high, this pin enables the internal VDD monitor, which forces a system reset when VDD is < 2.7 V. When tied low, the internal VDD monitor is disabled. In most applications, MONEN should be connected directly to VDD. VREF 12 7 A I/O Bandgap Voltage Reference Output (all devices). DAC Voltage Reference Input (C8051F041/3 only). VREFA 8 A In ADC0 (C8051F041/3/5/7) and ADC2 (C8051F041/3 only) Voltage Reference Input. VREF0 16 A In ADC0 Voltage Reference Input. VREF2 17 A In ADC2 Voltage Reference Input (C8051F040/2 only). VREF 15 A In DAC Voltage Reference Input (C8051F040/2 only). AIN0.0 18 9 A In ADC0 Input Channel 0 (See ADC0 Specification for com- plete description). |
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