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ADS8881IDRCT Datasheet(PDF) 4 Page - Texas Instruments |
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ADS8881IDRCT Datasheet(HTML) 4 Page - Texas Instruments |
4 / 44 page ADS8881 SBAS547A – MAY 2013 – REVISED JULY 2013 www.ti.com ELECTRICAL CHARACTERISTICS (continued) All minimum and maximum specifications are at TA = –40°C to +85°C, AVDD = 3 V, DVDD = 3 V, VREF = 5 V, VCM = VREF / 2 V, and fSAMPLE = 1 MSPS, unless otherwise noted. Typical specifications are at TA = +25°C, AVDD = 3 V, and DVDD = 3 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DYNAMIC CHARACTERISTICS At 1 kHz, VREF = 5 V 98 99.9 dB SINAD Signal-to-noise + distortion(6) At 10 kHz, VREF = 5 V 98.7 dB At 100 kHz, VREF = 5 V 93.3 dB At 1 kHz, VREF = 5 V 98.5 100 dB SNR Signal-to-noise ratio(6) At 10 kHz, VREF = 5 V 99.5 dB At 100 kHz, VREF = 5 V 93.5 dB At 1 kHz, VREF = 5 V –115 dB THD Total harmonic distortion(6)(7) At 10 kHz, VREF = 5 V –112 dB At 100 kHz, VREF = 5 V –102 dB At 1 kHz, VREF = 5 V 115 dB SFDR Spurious-free dynamic range(6) At 10 kHz, VREF = 5 V 112 dB At 100 kHz, VREF = 5 V 102 dB BW-3dB –3-dB small-signal bandwidth 30 MHz EXTERNAL REFERENCE INPUT VREF Input range 2.5 5 V Reference input current During conversion, 1-MHz sample rate, mid-code 350 μA Decoupling capacitor at the REF CREF 10 22 µF input POWER-SUPPLY REQUIREMENTS AVDD Analog supply 2.7 3 3.6 V Power-supply Digital supply range 1.65 3 3.6 V voltage DVDD Digital supply range for specified performance 2.7 3 3.6 V Supply current AVDD 1-MHz sample rate, AVDD = 3 V 1.8 2.4 mA 1-MHz sample rate, AVDD = 3 V 5.5 7.2 mW PVA Power dissipation 100-kHz sample rate, AVDD = 3 V 0.55 mW 10-kHz sample rate, AVDD = 3 V 55 μW IAPD Device power-down current(8) 50 nA LOGIC FAMILY (CMOS) VIH 0.7 × DVDD DVDD + 0.3 V Logic level (digital inputs) VIL –0.3 0.3 × DVDD V VOH IO = 500-μA source, CLOAD = 20 pF 0.8 × DVDD DVDD V Logic level (digital outputs) VOL IO = 500-μA sink, CLOAD = 20 pF 0 0.2 × DVDD V TEMPERATURE RANGE TA Operating free-air temperature –40 +85 °C (6) All specifications expressed in decibels (dB) refer to the full-scale input (FSR) and are tested with an input signal 0.5 dB below full-scale, unless otherwise specified. (7) Calculated on the first nine harmonics of the input frequency. (8) The device automatically enters a power-down state at the end of every conversion, and remains in power-down during the acquisition phase. 4 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: ADS8881 |
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