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EP2AGX45DF29C6N Datasheet(PDF) 29 Page - Altera Corporation |
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EP2AGX45DF29C6N Datasheet(HTML) 29 Page - Altera Corporation |
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29 / 90 page  Switching Characteristics This section provides performance characteristics of the Arria II GX and GZ core and periphery blocks for commercial grade devices. The following tables are considered final and are based on actual silicon characterization and testing. These numbers reflect the actual performance of the device under worst-case silicon process, voltage, and junction temperature conditions. Transceiver Performance Specifications Table 1–34 lists the Arria II GX transceiver specifications. Table 1–34. Transceiver Specifications for Arria II GX Devices (Note 1) (Part 1 of 7) Symbol/ Description Condition I3 C4 C5 and I5 C6 Unit Min Typ Max Min Typ Max Min Typ Max Min Typ Max Reference Clock Supported I/O Standards 1.2-V PCML, 1.5-V PCML, 2.5-V PCML, Differential LVPECL, LVDS, and HCSL Input frequency from REFCLK input pins — 50 — 622.08 50 — 622.08 50 — 622.08 50 — 622.08 MHz Input frequency from PLD input — 50 — 200 50 — 200 50 — 200 50 — 200 MHz Absolute VMAX for a REFCLK pin — — — 2.2 — — 2.2 — — 2.2 — — 2.2 V Absolute VMIN for a REFCLK pin — –0.3 — — –0.3 — — –0.3 — — –0.3 — — V Rise/fall time (2) — — — 0.2 — — 0.2 — — 0.2 — — 0.2 UI Duty cycle — 45 — 55 45 — 55 45 — 55 45 — 55 % Peak-to-peak differential input voltage — 200 — 2000 200 — 2000 200 — 2000 200 — 2000 mV Spread-spectrum modulating clock frequency PCIe 30 — 33 30 — 33 30 — 33 30 — 33 kHz |
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