EP2AGZ225HF40I3N datasheet(66/382 Pages) ALTERA

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EP2AGZ225HF40I3N Datasheet(PDF) 66 Page - Altera Corporation

Part #	EP2AGZ225HF40I3N

Description	Volume 1: Device Interfaces and Integration

Download	382 Pages

Scroll/Zoom	100%

Manufacturer	ALTERA [Altera Corporation]

Direct Link	http://www.altera.com

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66 / 382 page

3–18

Chapter 3: Memory Blocks in Arria II Devices

Memory Modes

Arria II Device Handbook Volume 1: Device Interfaces and Integration

December 2011

Altera Corporation

Figure 3–18 shows the memory block in shift-register mode.

ROM Mode

All Arria II memory blocks support ROM mode. A .mif initializes the ROM contents

of these blocks. The address lines of the ROM are registered on M9K and M144K

blocks; however, they can be unregistered on MLABs. The outputs can be registered

or unregistered. Output registers can be asynchronously cleared. The ROM read

operation is identical to the read operation in the single-port RAM configuration.

FIFO Mode

All memory blocks support FIFO mode. MLABs are ideal for designs with many

small, shallow FIFO buffers. To implement FIFO buffers in your design, you can use

the FIFO MegaWizard Plug-In Manager in the Quartus II software. Both single- and

dual-clock (asynchronous) FIFOs are supported.

f For more information about implementing FIFO buffers, refer to the SCFIFO and

DCFIFO Megafunctions User Guide.

1 MLABs do not support mixed-width FIFO mode.

Figure 3–18. Shift-Register Memory Configuration

w × m × n Shift Register

m-Bit Shift Register

n Number of Taps

Manufacturer	Part #	Datasheet	Description
Altera Corporation	EP2AGZ225	11Mb / 380P	Device Interfaces and Integration

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