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EP2C8T144I8N Datasheet(PDF) 5 Page - Altera Corporation

Part No. EP2C8T144I8N
Description  Cyclone II Device Handbook, Volume 1
Download  470 Pages
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Manufacturer  ALTERA [Altera Corporation]
Direct Link  http://www.altera.com
Logo ALTERA - Altera Corporation

EP2C8T144I8N Datasheet(HTML) 5 Page - Altera Corporation

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Cyclone II Device Handbook, Volume 1
Contents
Internal Timing ............................................................................................................................... 5–18
Cyclone II Clock Timing Parameters ........................................................................................... 5–23
Clock Network Skew Adders .......................................................................................................5–29
IOE Programmable Delay ............................................................................................................. 5–30
Default Capacitive Loading of Different I/O Standards .......................................................... 5–31
I/O Delays ....................................................................................................................................... 5–33
Maximum Input and Output Clock Rate .................................................................................... 5–46
High Speed I/O Timing Specifications ....................................................................................... 5–55
External Memory Interface Specifications .................................................................................. 5–63
JTAG Timing Specifications .......................................................................................................... 5–64
PLL Timing Specifications ............................................................................................................ 5–66
Duty Cycle Distortion ......................................................................................................................... 5–67
DCD Measurement Techniques ................................................................................................... 5–68
Referenced Documents ....................................................................................................................... 5–74
Document Revision History ............................................................................................................... 5–74
Chapter 6. Reference & Ordering Information
Software .................................................................................................................................................. 6–1
Device Pin-Outs ..................................................................................................................................... 6–1
Ordering Information ........................................................................................................................... 6–1
Document Revision History ................................................................................................................. 6–2
Section II. Clock Management
Revision History .................................................................................................................................... 6–1
Chapter 7. PLLs in Cyclone II Devices
Introduction ............................................................................................................................................ 7–1
Cyclone II PLL Hardware Overview .................................................................................................. 7–2
PLL Reference Clock Generation ................................................................................................... 7–6
Clock Feedback Modes ....................................................................................................................... 7–10
Normal Mode .................................................................................................................................. 7–10
Zero Delay Buffer Mode ................................................................................................................ 7–11
No Compensation Mode ............................................................................................................... 7–12
Source-Synchronous Mode ........................................................................................................... 7–13
Hardware Features .............................................................................................................................. 7–14
Clock Multiplication & Division .................................................................................................. 7–14
Programmable Duty Cycle ........................................................................................................... 7–15
Phase-Shifting Implementation .................................................................................................... 7–16
Control Signals ................................................................................................................................ 7–17
Manual Clock Switchover ............................................................................................................. 7–20
Clocking ................................................................................................................................................ 7–21
Global Clock Network ................................................................................................................... 7–21
Clock Control Block ....................................................................................................................... 7–24
Global Clock Network Clock Source Generation ...................................................................... 7–26
Global Clock Network Power Down ........................................................................................... 7–28


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