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EP2C8T144I8N Datasheet(PDF) 71 Page - Altera Corporation

Part No. EP2C8T144I8N
Description  Cyclone II Device Handbook, Volume 1
Download  470 Pages
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Manufacturer  ALTERA [Altera Corporation]
Direct Link  http://www.altera.com
Logo ALTERA - Altera Corporation

EP2C8T144I8N Datasheet(HTML) 71 Page - Altera Corporation

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Altera Corporation
2–45
February 2007
Cyclone II Device Handbook, Volume 1
Cyclone II Architecture
In Cyclone II devices, all the I/O banks support SDR and DDR SDRAM
memory up to 167 MHz/333 Mbps. All I/O banks support DQS signals
with the DQ bus modes of ×8/×9, or ×16/×18. Table 2–14 shows the
external memory interfaces supported in Cyclone II devices.
Cyclone II devices use data (DQ), data strobe (DQS), and clock pins to
interface with external memory. Figure 2–26 shows the DQ and DQS pins
in the ×8/×9 mode.
Table 2–14. External Memory Support in Cyclone II Devices
Note (1)
Memory Standard
I/O Standard
Maximum Bus
Width
Maximum Clock
Rate Supported
(MHz)
Maximum Data
Rate Supported
(Mbps)
SDR SDRAM
LVTTL (2)
72
167
167
DDR SDRAM
SSTL-2 class I (2)
72
167
333 (1)
SSTL-2 class II (2)
72
133
267 (1)
DDR2 SDRAM
SSTL-18 class I (2)
72
167
333 (1)
SSTL-18 class II (3)
72
125
250 (1)
QDRII SRAM (4)
1.8-V HSTL class I
(2)
36
167
668 (1)
1.8-V HSTL class II
(3)
36
100
400 (1)
Notes to Table 2–14:
(1)
The data rate is for designs using the Clock Delay Control circuitry.
(2)
The I/O standards are supported on all the I/O banks of the Cyclone II device.
(3)
The I/O standards are supported only on the I/O banks on the top and bottom of the Cyclone II device.
(4)
For maximum performance, Altera recommends using the 1.8-V HSTL I/O standard because of higher I/O drive
strength. QDRII SRAM devices also support the 1.5-V HSTL I/O standard.


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