74AUP2G06

All information provided in this document is subject to legal disclaimers.

© NXP B.V. 2011. All rights reserved.

Product data sheet

Rev. 4 — 6 December 2011

3 of 18

NXP Semiconductors

74AUP2G06

Low-power dual inverter with open-drain output

6.

Pinning information

6.1 Pinning

6.2 Pin description

7.

Functional description

7.1 Function table

[1]

H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF-state.

Fig 4.

Pin configuration SOT363

Fig 5.

Pin configuration SOT886

Fig 6.

Pin configuration SOT891,

SOT1115 and SOT1202

74AUP2G06

1A

1Y

GND

2A

2Y

001aal424

1

2

3

6

5

4

74AUP2G06

GND

001aal425

1A

2A

1Y

2Y

Transparent top view

2

3

1

5

4

6

74AUP2G06

GND

001aal426

1A

2A

1Y

2Y

Transparent top view

2

3

1

5

4

6

Table 3.

Pin description

Symbol

Pin

Description

1A, 2A

1, 3

data input

GND

2

ground (0 V)

1Y, 2Y

6, 4

data output

5

supply voltage

Table 4.

Function table[1]

Input nA

Output nY

LZ

HL