S25FL256SAGNFIQ00 datasheet(7/153 Pages) SPANSION

Part #	S25FL256SAGNFIQ00

Description	MirrorBit Flash Non-Volatile Memory CMOS 3.0 Volt Core with Versatile I/O Serial Peripheral Interface with Multi-I/O

Download	153 Pages

Scroll/Zoom	100%

Manufacturer	SPANSION [SPANSION]

Direct Link	http://www.spansion.com

Logo

7 / 153 page

July 12, 2012 S25FL128S_256S_00_05

S25FL128S and S25FL256S

7

Data

She e t

Figures

Figure 3.1

HOLD Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 3.2

Bus Master and Memory Devices on the SPI Bus - Single Bit Data Path . . . . . . . . . . . . . . . 20

Figure 3.3

Bus Master and Memory Devices on the SPI Bus - Dual Bit Data Path . . . . . . . . . . . . . . . . 20

Figure 3.4

Bus Master and Memory Devices on the SPI Bus - Quad Bit Data Path . . . . . . . . . . . . . . . . 20

Figure 4.1

SPI SDR Modes Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 4.2

SPI DDR Modes Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 4.3

Stand Alone Instruction Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 4.4

Single Bit Wide Input Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 4.5

Single Bit Wide Output Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 4.6

Single Bit Wide I/O Command without Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 4.7

Single Bit Wide I/O Command with Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 4.8

Dual Output Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 4.9

Quad Output Command without Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 4.10

Dual I/O Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 4.11

Quad I/O Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 4.12

DDR Fast Read with EHPLC = 00b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 4.13

DDR Dual I/O Read with EHPLC = 01b and DLP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 4.14

DDR Quad I/O Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 5.1

Maximum Negative Overshoot Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 5.2

Maximum Positive Overshoot Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 5.3

Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 5.4

Power-down and Voltage Drop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 6.1

Waveform Element Meanings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 6.2

Input, Output, and Timing Reference Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 6.3

Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 6.4

Reset Low at the End of POR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 6.5

Reset High at the End of POR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 6.6

POR followed by Hardware Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 6.7

Hardware Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 6.8

Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 6.9

SPI Single Bit Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 6.10

SPI Single Bit Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 6.11

SPI SDR MIO Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 6.12

Hold Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 6.13

WP# Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 6.14

SPI DDR Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Figure 6.15

SPI DDR Output Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Figure 6.16

SPI DDR Data Valid WIndow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Figure 7.1

16-Lead SOIC Package, Top View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Figure 7.2

Leadless Package (WSON), Top View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 7.3

24-Ball BGA, 5 x 5 Ball Footprint (FAB024), Top View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 7.4

24-Ball BGA, 4 x 6 Ball Footprint (FAC024), Top View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 8.1

OTP Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Figure 9.1

Advanced Sector Protection Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Figure 10.1

READ_ID Command Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Figure 10.2

Read Identification (RDID) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Figure 10.3

Read Electronic Signature (RES) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Figure 10.4

Read Status Register-1 (RDSR1) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Figure 10.5

Read Status Register-2 (RDSR2) Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Figure 10.6

Read Configuration Register (RDCR) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . 82

Figure 10.7

Read Bank Register (BRRD) Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Figure 10.8

Bank Register Write (BRWR) Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Figure 10.9

BRAC (B9h) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Figure 10.10 Write Registers (WRR) Command Sequence – 8 data bits . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Similar Part No. - S25FL256SAGNFIQ00

Manufacturer	Part #	Datasheet	Description
SPANSION	S25FL256SAGMFI000	5Mb / 153P	MirrorBit짰 Flash Non-Volatile Memory CMOS 3.0 Volt Core with Versatile I/O

More results

Similar Description - S25FL256SAGNFIQ00

Manufacturer	Part #	Datasheet	Description
SPANSION	S25FL128SAGMFIR01	5Mb / 153P	MirrorBit짰 Flash Non-Volatile Memory CMOS 3.0 Volt Core with Versatile I/O Serial Peripheral Interface with Multi-I/O
	S25FL128S	5Mb / 153P	MirrorBit짰 Flash Non-Volatile Memory CMOS 3.0 Volt Core with Versatile I/O Serial Peripheral Interface with Multi-I/O
	S25FL512S	5Mb / 143P	MirrorBit짰 Flash Non-Volatile Memory CMOS 3.0 Volt Core with Versatile I/O Serial Peripheral Interface with Multi-I/O
	S25FL128SAGMFI001	5Mb / 153P	CMOS 3.0 Volt Core with Versatile I/O Serial Peripheral Interface with Multi-I/O
	S25FL512SAGBHI313	1Mb / 140P	512 Mbit (64 Mbyte) MirrorBit짰 Flash Non-Volatile Memory CMOS 3.0 Volt Core with Versatile I/O Serial Peripheral Interface with Multi-I/O
	S25FL256SAGMFI000	5Mb / 153P	MirrorBit짰 Flash Non-Volatile Memory CMOS 3.0 Volt Core with Versatile I/O
	S25FL132K	3Mb / 85P	CMOS 3.0-Volt Flash Non-Volatile Memory Serial Peripheral Interface with Multi-I/O Industrial and Automotive Temperature
	S25FL116K	2Mb / 79P	16-Mbit CMOS 3.0-Volt Flash Non-Volatile Memory Serial Peripheral Interface with Multi-I/O and Industrial and Automotive Temperature
Cypress Semiconductor	S25FS128S	4Mb / 151P	1.8 V, Serial Peripheral Interface with Multi-I/O, MirrorBit짰 Non-Volatile Flash
SPANSION	S25FL064P	2Mb / 67P	64-Mbit CMOS 3.0 Volt Flash Memory with 104-MHz SPI (Serial Peripheral Interface) Multi I/O Bus

More results

S25FL256SAGNFIQ00 Datasheet(PDF) 7 Page - SPANSION

S25FL256SAGNFIQ00 Datasheet(HTML) 7 Page - SPANSION

Similar Part No. - S25FL256SAGNFIQ00

Similar Description - S25FL256SAGNFIQ00

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL