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ADT7320UCPZ-RL7 Datasheet(PDF) 4 Page - Analog Devices |
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ADT7320UCPZ-RL7 Datasheet(HTML) 4 Page - Analog Devices |
4 / 24 page ADT7320 Data Sheet Rev. 0 | Page 4 of 24 Parameter Min Typ Max Unit Test Conditions/Comments Shutdown Current Supply current in shutdown mode At 3.3 V 2.0 15 µA At 5.5 V 5.2 25 µA Power Dissipation, Normal Mode 700 µW VDD = 3.3 V, normal mode at 25°C Power Dissipation, 1 SPS Mode 150 µW Power dissipated for VDD = 3.3 V, TA = 25°C 1 Accuracy specification includes repeatability. 2 The equivalent 3 σ limits are ±0.15°C. This 3 σ specification is provided to enable comparison with other vendors who use these limits. 3 For higher accuracy at 5 V operation, contact Analog Devices, Inc. 4 Temperature hysteresis does not include repeatability. 5 Based on a floating average of 10 readings. 6 Drift includes solder heat resistance and lifetime test performed as per JEDEC Standard JESD22-A108. SPI TIMING SPECIFICATIONS TA = −40°C to +150°C, VDD = 2.7 V to 5.5 V, unless otherwise noted. All input signals are specified with rise time (tR) = fall time (tF) = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. Table 2. Parameter1, 2 Limit at TMIN, TMAX Unit Descriptions t1 0 ns min CS falling edge to SCLK active edge setup time t2 100 ns min SCLK high pulse width t3 100 ns min SCLK low pulse width t4 30 ns min Data setup time prior to SCLK rising edge t5 25 ns min Data hold time after SCLK rising edge t6 5 ns min Data access time after SCLK falling edge 60 ns max VDD = 4.5 V to 5.5 V 80 ns max VDD = 2.7 V to 3.6 V t73 10 ns min Bus relinquish time after CS inactive edge 80 ns max Bus relinquish time after CS inactive edge t8 0 ns min SCLK inactive edge to CS rising edge hold time t9 0 ns min CS falling edge to DOUT active time 60 ns max VDD = 4.5 V to 5.5 V 80 ns max VDD = 2.7 V to 3.6 V t10 10 ns min SCLK inactive edge to DOUT low 1 Sample tested during initial release to ensure compliance. 2 See Figure 2. 3 This means that the times quoted in the timing characteristics in Table 2 are the true bus relinquish times of the part and, as such, are independent of external bus loading capacitances. CS SCLK DIN DOUT t1 1 8 7 6 MSB LSB 2 3 MSB LSB 9 10 23 24 t2 t4 t5 t3 t6 t7 t8 t9 t10 Figure 2. Detailed SPI Timing Diagram |
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