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ACPL-C87B-000E Datasheet(PDF) 11 Page - AVAGO TECHNOLOGIES LIMITED |
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ACPL-C87B-000E Datasheet(HTML) 11 Page - AVAGO TECHNOLOGIES LIMITED |
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11 / 14 page  11 Figure 19. Typical application circuit. Definitions Gain Gain is defined as the slope of the best-fit line of differen- tial output voltage (VOUT+ – VOUT-) over the nominal input range, with offset error adjusted out. Nonlinearity Nonlinearity is defined as half of the peak-to-peak output deviation from the best-fit gain line, expressed as a per- centage of the full-scale differential output voltage. Common Mode Transient Immunity, CMTI, also known as Common Mode Rejection CMTI is tested by applying an exponentially rising/falling voltage step on pin 4 (GND1) with respect to pin 5 (GND2). The rise time of the test waveform is set to approximately 50 ns. The amplitude of the step is adjusted until the dif- ferential output (VOUT+ – VOUT-) exhibits more than a 200 mV deviation from the average output voltage for more than 1μs. The ACPL-C87x will continue to function if more than 10 kV/ s common mode slopes are applied, as long as the breakdown voltage limitations are observed. Power Supply Rejection, PSR PSRR is the ratio of differential amplitude of the ripple outputs over power supply ripple voltage, referred to the input, expressed in dB. Application Information Application Circuit The typical application circuit is shown in Figure 19. The ACPL-C87X voltage sensor is often used in photo- voltaic (PV) panel voltage measurement and tracking in PV inverters, and DC bus voltage monitoring in motor drivers. The high voltage across rails needs to be scaled down to fit the input range of the iso-amp by choosing R1 and R2 values according to appropriate ratio. The ACPL-C87X senses the single-ended input signal and produces differential outputs across the galvanic isolation barrier. The differential outputs (Vout+, Vout-) can be connected to an op-amp to convert to a single- ended signal or directly to two ADCs. The op-amp used in the external post-amplifier circuit should be of sufficiently high precision so that it does not contribute a significant amount of offset or offset drift relative to the contribu- tion from the isolation amplifier. Generally, op-amps with bipolar input stages exhibit better offset performance than op-amps with JFET or MOSFET input stages. In addition, the op-amp should also have enough bandwidth and slew rate so that it does not adversely affect the response speed of the overall circuit. The post- amplifier circuit includes a pair of capacitors (C4 and C5) that form a single-pole low-pass filter; these capacitors allow the bandwidth of the post-amp to be adjusted in- dependently of the gain and are useful for reducing the output noise from the isolation amplifier. The gain-setting resistors in the post-amp should have a tolerance of 1% or better to ensure adequate CMRR and adequate gain tolerance for the overall circuit. Resistor networks can be used that have much better ratio toler- ances than can be achieved using discrete resistors. A resistor network also reduces the total number of compo- nents for the circuit as well as the required board space. VDD1 1 VIN 2 SHDN 3 GND1 4 GND2 5 VOUT- 6 VOUT+ 7 VDD2 8 U1 ACPL-C87X GND2 R4 10K,1% GND2 VDD2 VDD1 Vout GND1 L1 L2 R2 10K C1 100 pF C2 100 nF C3 100 nF R3 10K,1% R1 U2 OPA237 V+ V- C4 100 pF R5 10K, 1% C5 100 pF R6 10K, 1% |
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