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AD7641 Datasheet(PDF) 5 Page - Analog Devices

Part # AD7641
Description  18-Bit, 5 MSPS PulSAR Differential ADC
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD7641 Datasheet(HTML) 5 Page - Analog Devices

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Data Sheet
AD7960
Rev. 0 | Page 5 of 24
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
Converting: Internal Reference Buffer
Disabled
Echoed clock mode, CNV± in
LVDS mode
46.5
56.2
mW
Converting: Internal Reference Buffer
Enabled
Echoed clock mode, CNV± in
LVDS mode
64.5
76.4
mW
Converting: Internal Reference Buffer
Disabled
Self clocked mode, CNV± in
CMOS mode7
39
47.4
mW
Power-Down
EN3 to EN0 = X000
7.2
94.5
µW
Energy per Conversion
Self clocked, CNV± in CMOS
mode7
7.8
9.5
nJ/sample
TEMPERATURE RANGE
Specified Performance
TMIN to TMAX
−40
+85
°C
1
The minimum and maximum values are guaranteed by characterization.
2
Using an external reference.
3
See Table 8 for logic levels of enable pins. When EN2 = 1, the −3 dB input bandwidth is 9 MHz. Use this lower bandwidth only when the throughput rate is 2 MSPS or
lower.
4
The REFIN pin is tied to 0 V in this mode.
5
The ANSI-644 LVDS specification has a minimum common-mode output (VOCM) of 1125 mV.
6
The current dissipated in the VCM circuitry when enabled is REF/20 kΩ and is not included in the operating currents listed.
7
CNV+ works as a CMOS input when CNV− is grounded. See Table 6 for additional information.
TIMING SPECIFICATIONS
VDD1 = 5 V; VDD2 = 1.8 V; VIO = 1.71 V to 1.89 V; REF = 5 V or 4.096 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
Symbol
Min
Typ
Max
Unit
Time Between Conversions
tCYC
200
ns
Acquisition Time
tACQ
tCYC − 100
ns
CNV± High Time
tCNVH
10
0.6 × tCYC
ns
CNV± to D± (MSB) Ready
tMSB
200
ns
CNV± to Last CLK± (LSB) Delay
tCLKL
160
ns
CLK± Period1
tCLK
3.33
4
(tCYC − tMSB + tCLKL)/n
ns
CLK± Frequency
fCLK
250
300
MHz
CLK± to DCO± Delay (Echoed Clock Mode)
tDCO
0
3
5
ns
DCO± to D± Delay (Echoed Clock Mode)
tD
0
1
ns
CLK± to D± Delay
tCLKD
0
3
5
ns
1
For the maximum CLK± period, the window available to read data is tCYC − tMSB + tCLKL. Divide this time by the number of bits (n) to be read, giving the maximum CLK±
frequency that can be used for a given conversion CNV± frequency. In echoed clock interface mode, n = 18; in self clocked interface mode, n = 20.


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