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IS61WV5128EDBLL-10BI Datasheet(PDF) 1 Page - Integrated Silicon Solution, Inc |
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IS61WV5128EDBLL-10BI Datasheet(HTML) 1 Page - Integrated Silicon Solution, Inc |
1 / 14 page Integrated Silicon Solution, Inc. — www.issi.com 1 Rev. B 11/08/2011 Copyright©2011IntegratedSiliconSolution,Inc.Allrightsreserved.ISSIreservestherighttomakechangestothisspecificationanditsproductsatanytimewithout notice.ISSIassumesnoliabilityarisingoutoftheapplicationoruseofanyinformation,productsorservicesdescribedherein.Customersareadvisedtoobtainthelat- estversionofthisdevicespecificationbeforerelyingonanypublishedinformationandbeforeplacingordersforproducts. IntegratedSiliconSolution,Inc.doesnotrecommendtheuseofanyofitsproductsinlifesupportapplicationswherethefailureormalfunctionoftheproductcanreason- ablybeexpectedtocausefailureofthelifesupportsystemortosignificantlyaffectitssafetyoreffectiveness.Productsarenotauthorizedforuseinsuchapplications unlessIntegratedSiliconSolution,Inc.receiveswrittenassurancetoitssatisfaction,that: a.)theriskofinjuryordamagehasbeenminimized; b.)theuserassumeallsuchrisks;and c.)potentialliabilityofIntegratedSiliconSolution,Incisadequatelyprotectedunderthecircumstances IS61WV5128EDBLL IS64WV5128EDBLL FEATURES • High-speedaccesstime:8,10ns • LowActivePower:85mW(typical) • LowStandbyPower:7mW(typical) CMOSstandby • Singlepowersupply —Vdd2.4Vto3.6V(10ns) —Vdd3.3V±10%(8ns) • Fullystaticoperation:noclockorrefresh required • Threestateoutputs • IndustrialandAutomotivetemperaturesupport • Lead-freeavailable • ErrorDetectionandErrorCorrection 512K x 8 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM WITH ECC DESCRIPTION The ISSI IS61/64WV5128EDBLL is ahigh-speed, 4,194,304-bitstaticRAMsorganizedas524,288wordsby 8bits.Itisfabricatedusing ISSI'shigh-performanceCMOS technology.Thishighlyreliableprocesscoupledwithinno- vativecircuitdesigntechniques,yieldshigh-performance andlowpowerconsumptiondevices. When CE is HIGH (deselected), the device assumes a standbymodeatwhichthepowerdissipationcanbere- duceddownwithCMOSinputlevels. EasymemoryexpansionisprovidedbyusingChipEnable andOutputEnableinputs,CEandOE.TheactiveLOW WriteEnable(WE)controlsbothwritingandreadingof thememory. TheIS61/64WV5128EDBLLispackagedintheJEDEC standard44-pinTSOP-II,36-pinSOJand36-pinMiniBGA (6mmx8mm). FUNCTIONAL BLOCK DIAGRAM NOVEMBER 2011 Memory Array (512Kx8) ECC Array (512Kx4) Decoder I/O Data Circuit ECC Column I/O 8 8 12 8 4 Control Circuit /CE /OE /WE IO0-7 A0-A18 |
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