Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.NET

X  

IS43DR16320B-3DBI Datasheet(PDF) 11 Page - Integrated Silicon Solution, Inc

Part # IS43DR16320B-3DBI
Description  512Mb (x8, x16) DDR2 SDRAM
Download  30 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  ISSI [Integrated Silicon Solution, Inc]
Direct Link  http://www.issi.com
Logo ISSI - Integrated Silicon Solution, Inc

IS43DR16320B-3DBI Datasheet(HTML) 11 Page - Integrated Silicon Solution, Inc

Back Button IS43DR16320B-3DBI Datasheet HTML 7Page - Integrated Silicon Solution, Inc IS43DR16320B-3DBI Datasheet HTML 8Page - Integrated Silicon Solution, Inc IS43DR16320B-3DBI Datasheet HTML 9Page - Integrated Silicon Solution, Inc IS43DR16320B-3DBI Datasheet HTML 10Page - Integrated Silicon Solution, Inc IS43DR16320B-3DBI Datasheet HTML 11Page - Integrated Silicon Solution, Inc IS43DR16320B-3DBI Datasheet HTML 12Page - Integrated Silicon Solution, Inc IS43DR16320B-3DBI Datasheet HTML 13Page - Integrated Silicon Solution, Inc IS43DR16320B-3DBI Datasheet HTML 14Page - Integrated Silicon Solution, Inc IS43DR16320B-3DBI Datasheet HTML 15Page - Integrated Silicon Solution, Inc Next Button
Zoom Inzoom in Zoom Outzoom out
 11 / 30 page
background image
IS43/46DR86400B, IS43/46DR16320B
Integrated Silicon Solution, Inc. – www.issi.com –
11
Rev. I, 8/01/2012
Commands
DESELECT
The DESELECT function (CS# HIGH) prevents new commands from being executed by the DDR2 SDRAM. The DDR2 SDRAM is
effectively deselected. Operations already in progress are not affected. DESELECT is also referred to as COMMAND INHIBIT.
NO OPERATION (NOP)
The NO OPERATION (NOP) command is used to instruct the selected DDR2 SDRAM to perform a NOP (CS# is LOW; RAS#, CAS#, and
WE# are HIGH). This prevents unwanted commands from being registered during idle or wait states. Operations already in progress
are not affected.
LOAD MODE (LM)
The mode registers are loaded via bank address and address inputs. The bank address balls determine which mode register will be
programmed. See “Mode Register (MR)” in the next section. The LM command can only be issued when all banks are idle, and a
subsequent executable command cannot be issued until tMRD is met.
ACTIVATE
The ACTIVATE command is used to open (or activate) a row in a particular bank for a subsequent access. The value on the bank
address inputs determines the bank, and the address inputs select the row. This row will remains active (or open) for accesses until a
PRECHARGE command is issued to that bank. A PRECHARGE command must be issued before opening a different row in the same
bank.
READ
The READ command is used to initiate a burst read access to an active row. The value on the bank address inputs determine the
bank, and the address provided on address inputs A0–A9 selects the starting column location. The value on input A10 determines
whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the
READ burst; if auto precharge is not selected, the row will remain open for subsequent accesses. DDR2 SDRAM also supports the AL
feature, which allows a READ or WRITE command to be issued prior to tRCD(Min) by delaying the actual registration of the
READ/WRITE command to the internal device by AL clock cycles.
WRITE
The WRITE command is used to initiate a burst write access to an active row. The value on the bank select inputs selects the bank,
and the address provided on inputs A0–A9 selects the starting column location. The value on input A10 determines whether or not
auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the WRITE burst; if
auto precharge is not selected, the row will remain open for subsequent accesses.
DDR2 SDRAM also supports the AL feature, which allows a READ or WRITE command to be issued prior to tRCD(MIN) by delaying the
actual registration of the READ/WRITE command to the internal device by AL clock cycles. Input data appearing on the DQ is written
to the memory array subject to the DM input logic level appearing coincident with the data. If a given DM signal is registered LOW,
the corresponding data will be written to memory; if the DM signal is registered HIGH, the corresponding data inputs will be ignored,
and a WRITE will not be executed to that byte/column location.
PRECHARGE
The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be
available for a subsequent row activation a specified time (tRP) after the PRECHARGE command is issued, except in the case of
concurrent auto precharge, where a READ or WRITE command to a different bank is allowed as long as it does not interrupt the data
transfer in the current bank and does not violate any other timing parameters. After a bank has been precharged, it is in the idle
state and must be activated prior to any READ or WRITE commands being issued to that bank. A PRECHARGE command is allowed if
there is no open row in that bank (idle state) or if the previously open row is already in the process of precharging. However, the
precharge period will be determined by the last PRECHARGE command issued to the bank.
REFRESH
REFRESH is used during normal operation of the DDR2 SDRAM and is analogous to CAS#-before-RAS# (CBR) REFRESH. All banks must
be in the idle mode prior to issuing a REFRESH command. This command is nonpersistent, so it must be issued each time a refresh is


Similar Part No. - IS43DR16320B-3DBI

ManufacturerPart #DatasheetDescription
logo
Integrated Silicon Solu...
IS43DR16320 ISSI-IS43DR16320 Datasheet
867Kb / 29P
   Clock frequency up to 400MHz
IS43DR16320D ISSI-IS43DR16320D Datasheet
1Mb / 48P
   Differential data strobe
More results

Similar Description - IS43DR16320B-3DBI

ManufacturerPart #DatasheetDescription
logo
Integrated Silicon Solu...
IS43DR86400 ISSI-IS43DR86400 Datasheet
867Kb / 29P
   512Mb (x8, x16) DDR2 SDRAM
IS43DR86400B ISSI-IS43DR86400B Datasheet
760Kb / 29P
   512Mb (x8, x16) DDR2 SDRAM
logo
Micron Technology
MT47H32M16CC3B MICRON-MT47H32M16CC3B Datasheet
2Mb / 133P
   512Mb: x4, x8, x16 DDR2 SDRAM
MT47H64M8B6-25ELDTR MICRON-MT47H64M8B6-25ELDTR Datasheet
2Mb / 133P
   512Mb: x4, x8, x16 DDR2 SDRAM
MT48LC128M4A2 MICRON-MT48LC128M4A2_07 Datasheet
2Mb / 68P
   512Mb x4, x8, x16 SDRAM
logo
Integrated Silicon Solu...
IS43DR81280A ISSI-IS43DR81280A Datasheet
855Kb / 28P
   1Gb (x8, x16) DDR2 SDRAM
IS43DR81280 ISSI-IS43DR81280 Datasheet
863Kb / 28P
   1Gb (x8, x16) DDR2 SDRAM
IS43DR81280B ISSI-IS43DR81280B Datasheet
549Kb / 28P
   1Gb (x8, x16) DDR2 SDRAM
logo
Micron Technology
MT47H16M16BG-3ITB MICRON-MT47H16M16BG-3ITB Datasheet
1Mb / 129P
   256Mb: x4, x8, x16 DDR2 SDRAM
MT47H64M16HR-25ELH MICRON-MT47H64M16HR-25ELH Datasheet
1Mb / 132P
   1Gb: x4, x8, x16 DDR2 SDRAM
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30


Datasheet Download

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEET.NET
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com