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PIC18F2525 Datasheet(PDF) 65 Page - Microchip Technology

Part # PIC18F2525
Description  28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

PIC18F2525 Datasheet(HTML) 65 Page - Microchip Technology

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© 2008 Microchip Technology Inc.
DS39626E-page 63
PIC18F2525/2620/4525/4620
TABLE 5-2:
REGISTER FILE SUMMARY (PIC18F2525/2620/4525/4620)
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Details on
page:
TOSU
Top-of-Stack Upper Byte (TOS<20:16>)
---0 0000
49, 54
TOSH
Top-of-Stack High Byte (TOS<15:8>)
0000 0000
49, 54
TOSL
Top-of-Stack Low Byte (TOS<7:0>)
0000 0000
49, 54
STKPTR
STKFUL(6)
STKUNF(6)
SP4
SP3
SP2
SP1
SP0
00-0 0000
49, 55
PCLATU
Holding Register for PC<20:16>
---0 0000
49, 54
PCLATH
Holding Register for PC<15:8>
0000 0000
49, 54
PCL
PC Low Byte (PC<7:0>)
0000 0000
49, 54
TBLPTRU
bit 21
Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)
--00 0000
49, 82
TBLPTRH
Program Memory Table Pointer High Byte (TBLPTR<15:8>)
0000 0000
49, 82
TBLPTRL
Program Memory Table Pointer Low Byte (TBLPTR<7:0>)
0000 0000
49, 82
TABLAT
Program Memory Table Latch
0000 0000
49, 82
PRODH
Product Register High Byte
xxxx xxxx
49, 89
PRODL
Product Register Low Byte
xxxx xxxx
49, 89
INTCON
GIE/GIEH
PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 000x
49, 111
INTCON2
RBPU
INTEDG0
INTEDG1
INTEDG2
—TMR0IP
—RBIP
1111 -1-1
49, 112
INTCON3
INT2IP
INT1IP
INT2IE
INT1IE
INT2IF
INT1IF
11-0 0-00
49, 113
INDF0
Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register)
N/A
49, 68
POSTINC0
Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register)
N/A
49, 68
POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register)
N/A
49, 68
PREINC0
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register)
N/A
49, 68
PLUSW0
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) –
value of FSR0 offset by W
N/A
49, 68
FSR0H
Indirect Data Memory Address Pointer 0 High Byte
---- 0000
49, 68
FSR0L
Indirect Data Memory Address Pointer 0 Low Byte
xxxx xxxx
49, 68
WREG
Working Register
xxxx xxxx
49
INDF1
Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register)
N/A
49, 68
POSTINC1
Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register)
N/A
49, 68
POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register)
N/A
49, 68
PREINC1
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register)
N/A
49, 68
PLUSW1
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) –
value of FSR1 offset by W
N/A
49, 68
FSR1H
Indirect Data Memory Address Pointer 1 High Byte
---- 0000
50, 68
FSR1L
Indirect Data Memory Address Pointer 1 Low Byte
xxxx xxxx
50, 68
BSR
Bank Select Register
---- 0000
50, 59
INDF2
Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register)
N/A
50, 68
POSTINC2
Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register)
N/A
50, 68
POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register)
N/A
50, 68
PREINC2
Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register)
N/A
50, 68
PLUSW2
Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) –
value of FSR2 offset by W
N/A
50, 68
FSR2H
Indirect Data Memory Address Pointer 2 High Byte
---- 0000
50, 68
FSR2L
Indirect Data Memory Address Pointer 2 Low Byte
xxxx xxxx
50, 68
STATUS
—N
OV
Z
DC
C
---x xxxx
50, 66
Legend:
x
= unknown, u = unchanged, — = unimplemented, q = value depends on condition
Note
1:
The SBOREN bit is only available when the BOREN1:BOREN0 Configuration bits = 01; otherwise, it is disabled and reads as ‘0’. See
Section 4.4 “Brown-out Reset (BOR)”.
2:
These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices;
individual unimplemented bits should be interpreted as ‘-’.
3:
The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘0’. See Section 2.6.4 “PLL in
INTOSC Modes”.
4:
The RE3 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit = 0); otherwise, RE3 reads as ‘0’. This bit is
read-only.
5:
RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes.
When disabled, these bits read as ‘0’.
6:
Bit 7 and bit 6 are cleared by user software or by a POR.


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