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PIC18F2525 Datasheet(PDF) 66 Page - Microchip Technology

Part # PIC18F2525
Description  28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

PIC18F2525 Datasheet(HTML) 66 Page - Microchip Technology

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PIC18F2525/2620/4525/4620
DS39626E-page 64
© 2008 Microchip Technology Inc.
TMR0H
Timer0 Register High Byte
0000 0000
50, 125
TMR0L
Timer0 Register Low Byte
xxxx xxxx
50, 125
T0CON
TMR0ON
T08BIT
T0CS
T0SE
PSA
T0PS2
T0PS1
T0PS0
1111 1111
50, 123
OSCCON
IDLEN
IRCF2
IRCF1
IRCF0
OSTS
IOFS
SCS1
SCS0
0100 q000
30, 50
HLVDCON
VDIRMAG
IRVST
HLVDEN
HLVDL3
HLVDL2
HLVDL1
HLVDL0
0-00 0101
50, 243
WDTCON
—SWDTEN
--- ---0
50, 259
RCON
IPEN
SBOREN(1)
—RI
TO
PD
POR
BOR
0q-1 11q0
42, 48, 120
TMR1H
Timer1 Register High Byte
xxxx xxxx
50, 131
TMR1L
Timer1 Register Low Byte
xxxx xxxx
50, 131
T1CON
RD16
T1RUN
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
TMR1CS
TMR1ON
0000 0000
50, 127
TMR2
Timer2 Register
0000 0000
50, 134
PR2
Timer2 Period Register
1111 1111
50, 134
T2CON
T2OUTPS3
T2OUTPS2
T2OUTPS1
T2OUTPS0
TMR2ON
T2CKPS1
T2CKPS0
-000 0000
50, 133
SSPBUF
MSSP Receive Buffer/Transmit Register
xxxx xxxx
50, 169,
170
SSPADD
MSSP Address Register in I2C™ Slave Mode. MSSP Baud Rate Reload Register in I2C Master Mode.
0000 0000
50, 170
SSPSTAT
SMP
CKE
D/A
PS
R/W
UA
BF
0000 0000
50, 162,
171
SSPCON1
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
0000 0000
50, 163,
172
SSPCON2
GCEN
ACKSTAT
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
0000 0000
50, 173
ADRESH
A/D Result Register High Byte
xxxx xxxx
51, 232
ADRESL
A/D Result Register Low Byte
xxxx xxxx
51, 232
ADCON0
CHS3
CHS2
CHS1
CHS0
GO/DONE
ADON
--00 0000
51, 223
ADCON1
VCFG1
VCFG0
PCFG3
PCFG2
PCFG1
PCFG0
--00 0qqq
51, 224
ADCON2
ADFM
ACQT2
ACQT1
ACQT0
ADCS2
ADCS1
ADCS0
0-00 0000
51, 225
CCPR1H
Capture/Compare/PWM Register 1 High Byte
xxxx xxxx
51, 140
CCPR1L
Capture/Compare/PWM Register 1 Low Byte
xxxx xxxx
51, 140
CCP1CON
P1M1(2)
P1M0(2)
DC1B1
DC1B0
CCP1M3
CCP1M2
CCP1M1
CCP1M0
0000 0000
51, 139,
147
CCPR2H
Capture/Compare/PWM Register 2 High Byte
xxxx xxxx
51, 140
CCPR2L
Capture/Compare/PWM Register 2 Low Byte
xxxx xxxx
51, 140
CCP2CON
DC2B1
DC2B0
CCP2M3
CCP2M2
CCP2M1
CCP2M0
--00 0000
51, 139
BAUDCON
ABDOVF
RCIDL
RXDTP
TXCKP
BRG16
WUE
ABDEN
0100 0-00
51, 204
PWM1CON
PRSEN
PDC6(2)
PDC5(2)
PDC4(2)
PDC3(2)
PDC2(2)
PDC1(2)
PDC0(2)
0000 0000
51, 156
ECCP1AS
ECCPASE
ECCPAS2
ECCPAS1
ECCPAS0
PSSAC1
PSSAC0
PSSBD1(2)
PSSBD0(2)
0000 0000
51, 157
CVRCON
CVREN
CVROE
CVRR
CVRSS
CVR3
CVR2
CVR1
CVR0
0000 0000
51, 239
CMCON
C2OUT
C1OUT
C2INV
C1INV
CIS
CM2
CM1
CM0
0000 0111
51, 233
TMR3H
Timer3 Register High Byte
xxxx xxxx
51, 137
TMR3L
Timer3 Register Low Byte
xxxx xxxx
51, 137
T3CON
RD16
T3CCP2
T3CKPS1
T3CKPS0
T3CCP1
T3SYNC
TMR3CS
TMR3ON
0000 0000
51, 135
TABLE 5-2:
REGISTER FILE SUMMARY (PIC18F2525/2620/4525/4620) (CONTINUED)
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Details on
page:
Legend:
x
= unknown, u = unchanged, — = unimplemented, q = value depends on condition
Note
1:
The SBOREN bit is only available when the BOREN1:BOREN0 Configuration bits = 01; otherwise, it is disabled and reads as ‘0’. See
Section 4.4 “Brown-out Reset (BOR)”.
2:
These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices;
individual unimplemented bits should be interpreted as ‘-’.
3:
The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘0’. See Section 2.6.4 “PLL in
INTOSC Modes”.
4:
The RE3 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit = 0); otherwise, RE3 reads as ‘0’. This bit is
read-only.
5:
RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes.
When disabled, these bits read as ‘0’.
6:
Bit 7 and bit 6 are cleared by user software or by a POR.


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