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AD9240ASZRL Datasheet(PDF) 9 Page - Analog Devices |
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AD9240ASZRL Datasheet(HTML) 9 Page - Analog Devices |
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9 / 24 page  AD9240 REV. –9– The addition of a differential input structure gives the user an additional level of flexibility that is not possible with traditional flash converters. The input stage allows the user to easily con- figure the inputs for either single-ended operation or differential operation. The A/D’s input structure allows the dc offset of the input signal to be varied independently of the input span of the converter. Specifically, the input to the A/D core is the differ- ence of the voltages applied at the VINA and VINB input pins. Therefore, the equation, VCORE = VINA – VINB (1) defines the output of the differential input stage and provides the input to the A/D core. The voltage, VCORE, must satisfy the condition, –VREF ≤ V CORE ≤ VREF (2) where VREF is the voltage at the VREF pin. While an infinite combination of VINA and VINB inputs exist that satisfy Equation 2, there is an additional limitation placed on the inputs by the power supply voltages of the AD9240. The power supplies bound the valid operating range for VINA and VINB. The condition, AVSS – 0.3 V < VINA < AVDD + 0.3 V (3) AVSS – 0.3 V < VINB < AVDD + 0.3 V where AVSS is nominally 0 V and AVDD is nominally +5 V, defines this requirement. Thus, the range of valid inputs for VINA and VINB is any combination that satisfies both Equa- tions 2 and 3. For additional information showing the relationship between VINA, VINB, VREF and the digital output of the AD9240, see Table IV. Refer to Table I and Table II for a summary of the various analog input and reference configurations. ANALOG INPUT OPERATION Figure 24 shows the equivalent analog input of the AD9240 which consists of a differential sample-and-hold amplifier (SHA). The differential input structure of the SHA is highly flexible, allowing the devices to be easily configured for either a differen- tial or single-ended input. The dc offset, or common-mode voltage, of the input(s) can be set to accommodate either single- supply or dual supply systems. Note also that the analog inputs, VINA and VINB, are interchangeable with the exception that reversing the inputs to the VINA and VINB pins results in a polarity inversion. VINA VINB CPIN+ CPAR CPIN– CPAR QS1 QS1 QH1 CS CS CH CH QS2 QS2 Figure 24. Simplified Input Circuit The input SHA of the AD9240 is optimized to meet the perfor- mance requirements for some of the most demanding commu- nication, imaging, and data acquisition applications while maintaining low power dissipation. Figure 25 is a graph of the full-power bandwidth of the AD9240, typically 60 MHz. Note that the small signal bandwidth is the same as the full-power bandwidth. The settling time response to a full-scale stepped input is shown in Figure 26 and is typically less than 40 ns to 0.0025%. The low input referred noise of 0.36 LSB’s rms is displayed via a grounded histogram and is shown in Figure 13. FREQUENCY – MHz 1 0 –7 1 10 100 –3 –4 –5 –6 –1 –2 –8 –9 –10 Figure 25. Full-Power Bandwidth SETTLING TIME – ns 16000 12000 0 0 60 10 20 30 40 50 8000 4000 70 80 Figure 26. Settling Time The SHA’s optimum distortion performance for a differential or single-ended input is achieved under the following two condi- tions: (1) the common-mode voltage is centered around mid- supply (i.e., AVDD/2 or approximately 2.5 V) and (2) the input signal voltage span of the SHA is set at its lowest (i.e., 2 V input span). This is due to the sampling switches, QS1, being CMOS switches whose RON resistance is very low but has some signal dependency which causes frequency dependent ac distortion while the SHA is in the track mode. The RON resistance of a CMOS switch is typically lowest at its midsupply but increases symmetrically as the input signal approaches either AVDD or AVSS. A lower input signal voltage span centered at midsupply reduces the degree of RON modulation. B |
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