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C8051F854-B-GU Datasheet(PDF) 5 Page - Silicon Laboratories |
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C8051F854-B-GU Datasheet(HTML) 5 Page - Silicon Laboratories |
5 / 290 page C8051F85x/86x Preliminary Rev 0.6 5 20.6.PCA Control Registers...............................................................................................160 21.Port I/O (Port 0, Port 1, Port 2, Crossbar, and Port Match) ..........................................178 21.1.General Port I/O Initialization.....................................................................................179 21.2.Assigning Port I/O Pins to Analog and Digital Functions ...........................................180 21.2.1.Assigning Port I/O Pins to Analog Functions.....................................................180 21.2.2.Assigning Port I/O Pins to Digital Functions......................................................180 21.2.3.Assigning Port I/O Pins to Fixed Digital Functions ............................................181 21.3.Priority Crossbar Decoder..........................................................................................182 21.4.Port I/O Modes of Operation......................................................................................184 21.4.1.Configuring Port Pins For Analog Modes ..........................................................184 21.4.2.Configuring Port Pins For Digital Modes ...........................................................184 21.4.3.Port Drive Strength............................................................................................184 21.5.Port Match..................................................................................................................185 21.6.Direct Read/Write Access to Port I/O Pins.................................................................185 21.7.Port I/O and Pin Configuration Control Registers ......................................................186 22.Reset Sources and Supply Monitor ...............................................................................204 22.1.Power-On Reset ........................................................................................................205 22.2.Power-Fail Reset / Supply Monitor ............................................................................206 22.3.Enabling the VDD Monitor .........................................................................................206 22.4.External Reset ...........................................................................................................207 22.5.Missing Clock Detector Reset....................................................................................207 22.6.Comparator0 Reset....................................................................................................207 22.7.Watchdog Timer Reset ..............................................................................................207 22.8.Flash Error Reset.......................................................................................................207 22.9.Software Reset ..........................................................................................................207 22.10.Reset Sources Control Registers.............................................................................208 23.Serial Peripheral Interface (SPI0) ...................................................................................214 23.1.Signal Descriptions ....................................................................................................215 23.1.1.Master Out, Slave In (MOSI) .............................................................................215 23.1.2.Master In, Slave Out (MISO) .............................................................................215 23.1.3.Serial Clock (SCK).............................................................................................215 23.1.4.Slave Select (NSS)............................................................................................215 23.2.SPI0 Master Mode Operation ....................................................................................216 23.3.SPI0 Slave Mode Operation ......................................................................................218 23.4.SPI0 Interrupt Sources...............................................................................................218 23.5.Serial Clock Phase and Polarity.................................................................................218 23.6.SPI Special Function Registers .................................................................................220 23.7.SPI Control Registers ................................................................................................224 24.System Management Bus / I2C (SMBus0) .....................................................................229 24.1.Supporting Documents ..............................................................................................230 24.2.SMBus Configuration.................................................................................................230 24.3.SMBus Operation.......................................................................................................230 24.3.1.Transmitter vs. Receiver....................................................................................231 24.3.2.Arbitration ..........................................................................................................231 24.3.3.Clock Low Extension .........................................................................................231 24.3.4.SCL Low Timeout..............................................................................................231 |
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