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A3PN250Z1QNG100ES Datasheet(PDF) 7 Page - Microsemi Corporation |
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A3PN250Z1QNG100ES Datasheet(HTML) 7 Page - Microsemi Corporation |
7 / 114 page Revision 11 1-1 1 – ProASIC3 nano Device Overview General Description ProASIC3, the third-generation family of Microsemi flash FPGAs, offers performance, density, and features beyond those of the ProASICPLUS® family. Nonvolatile flash technology gives ProASIC3 nano devices the advantage of being a secure, low power, single-chip solution that is Instant On. ProASIC3 nano devices are reprogrammable and offer time-to-market benefits at an ASIC-level unit cost. These features enable designers to create high-density systems using existing ASIC or FPGA design flows and tools. ProASIC3 nano devices offer 1 kbit of on-chip, reprogrammable, nonvolatile FlashROM storage as well as clock conditioning circuitry based on an integrated phase-locked loop (PLL). A3PN030 and smaller devices do not have PLL or RAM support. ProASIC3 nano devices have up to 250,000 system gates, supported with up to 36 kbits of true dual-port SRAM and up to 71 user I/Os. ProASIC3 nano devices increase the breadth of the ProASIC3 product line by adding new features and packages for greater customer value in high volume consumer, portable, and battery-backed markets. Added features include smaller footprint packages designed with two-layer PCBs in mind, low power, hot-swap capability, and Schmitt trigger for greater flexibility in low-cost and power-sensitive applications. Flash Advantages Reduced Cost of Ownership Advantages to the designer extend beyond low unit cost, performance, and ease of use. Unlike SRAM- based FPGAs, flash-based ProASIC3 nano devices allow all functionality to be Instant On; no external boot PROM is required. On-board security mechanisms prevent access to all the programming information and enable secure remote updates of the FPGA logic. Designers can perform secure remote in-system reprogramming to support future design iterations and field upgrades with confidence that valuable intellectual property (IP) cannot be compromised or copied. Secure ISP can be performed using the industry-standard AES algorithm. The ProASIC3 nano device architecture mitigates the need for ASIC migration at higher user volumes. This makes the ProASIC3 nano device a cost-effective ASIC replacement solution, especially for applications in the consumer, networking/communications, computing, and avionics markets. With a variety of devices under $1, ProASIC3 nano FPGAs enable cost-effective implementation of programmable logic and quick time to market. Security Nonvolatile, flash-based ProASIC3 nano devices do not require a boot PROM, so there is no vulnerable external bitstream that can be easily copied. ProASIC3 nano devices incorporate FlashLock, which provides a unique combination of reprogrammability and design security without external overhead, advantages that only an FPGA with nonvolatile flash programming can offer. ProASIC3 nano devices utilize a 128-bit flash-based lock and a separate AES key to provide the highest level of protection in the FPGA industry for programmed intellectual property and configuration data. In addition, all FlashROM data in ProASIC3 nano devices can be encrypted prior to loading, using the industry-leading AES-128 (FIPS192) bit block cipher encryption standard. The AES standard was adopted by the National Institute of Standards and Technology (NIST) in 2000 and replaces the 1977 DES standard. ProASIC3 nano devices have a built-in AES decryption engine and a flash-based AES key that make them the most comprehensive programmable logic device security solution available today. ProASIC3 nano devices with AES-based security provide a high level of protection for remote field updates over public networks such as the Internet, and are designed to ensure that valuable IP remains out of the hands of system overbuilders, system cloners, and IP thieves. |
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