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HUFA75631SK8 Datasheet(PDF) 6 Page - Fairchild Semiconductor

Part # HUFA75631SK8
Description  5.5A, 100V, 0.039 Ohm, N-Channel, UltraFET Power MOSFET
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Manufacturer  FAIRCHILD [Fairchild Semiconductor]
Direct Link  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

HUFA75631SK8 Datasheet(HTML) 6 Page - Fairchild Semiconductor

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©2001 Fairchild Semiconductor Corporation
HUFA75631SK8 Rev. B
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, TJM, and the
thermal resistance of the heat dissipating path determines the
maximum allowable device power dissipation, PDM, in an
application. Therefore the application’s ambient temperature,
TA (
oC), and thermal resistance RθJA (oC/W) must be reviewed
to ensure that TJM is never exceeded. Equation 1
mathematically represents the relationship and serves as the
basis for establishing the rating of the part.
In using surface mount devices such as the SOP-8 package,
the environment in which it is applied will have a significant
influence on the part’s current and maximum power
dissipation ratings. Precise determination of PDM is complex
and influenced by many factors:
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.
2. The number of copper layers and the thickness of the board.
3. The use of external heat sinks.
4. The use of thermal vias.
5. Air flow and board orientation.
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
Fairchild provides thermal information to assist the
designer’s preliminary application evaluation. Figure 20
defines the RθJA for the device as a function of the top
copper (component side) area. This is for a horizontally
positioned FR-4 board with 1oz copper after 1000 seconds
of steady state power with no air flow. This graph provides
the necessary information for calculation of the steady state
FIGURE 16. GATE CHARGE TEST CIRCUIT
FIGURE 17. GATE CHARGE WAVEFORMS
FIGURE 18. SWITCHING TIME TEST CIRCUIT
FIGURE 19. SWITCHING TIME WAVEFORM
Test Circuits and Waveforms (Continued)
RL
VGS
+
-
VDS
VDD
DUT
Ig(REF)
VDD
Qg(TH)
VGS = 2V
Qg(10)
VGS = 10V
Qg(TOT)
VGS = 20V
VDS
VGS
Ig(REF)
0
0
Qgs
Qgd
VGS
RL
RGS
DUT
+
-
VDD
VDS
VGS
tON
td(ON)
tr
90%
10%
VDS
90%
10%
tf
td(OFF)
tOFF
90%
50%
50%
10%
PULSE WIDTH
VGS
0
0
(EQ. 1)
P
DM
T
JM
T
A
()
ZθJA
-------------------------------
=
HUFA75631SK8


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