3/9

www.rohm.com

2010.06 - Rev.A

© 2010 ROHM Co., Ltd. All rights reserved.

Technical Note

BD3843FS,BD3841FS

●

Timing chart

1. Signal timing standards

・

Data is read at the rise of clock.

・

Latch is read at the fall of clock.

・

End latch signal at LOW.

* To avoid malfunctions, clock and data signals must terminate with the LOW state.

1byte=17bit

Fig.1

Parameter

Symbol

Limit

Unit

Min.

Typ.

Max.

Minimum clock width

twc

2.0

－

－

µs

Minimum data width

twd

2.0

－

－

µs

Minimum latch width

twl

2.0

－

－

µs

LOW hold width

twh

2.0

－

－

µs

Data setup time (DATA→CLK)

tsd

1.0

－

－

µs

Data hold time (CLK→DATA)

thd

1.0

－

－

µs

Latch setup time (CLK→LATCH)

tsl

1.0

－

－

µs

Latch hold time (DATA→LATCH)

thl

1.0

－

－

µs

Latch low setup time

ts

1.0

－

－

µs

Latch low hold time

th

1.0

－

－

µs

2. Voltage standards of control signal

Parameter

Conditions

Limits

Unit

Min.

Typ.

Max.(≦Vcc)

“H” input voltage

Vcc=5～7.3V

VEE=-5～-7.3V

2.2

－

5.5

V

“L” input voltage

0

－

1.0

V

CL

（CLOCK）

DA

DATA

LATCH

thd

thd

th

ts

tsl

thl

tsd

twc

twh

twd

twl

tsu

DATA

DATA

LATCH

90％

90％

90％

90％

10％

10％

10％

90％

90％

90％

90％

90％

10％

10％

10％

twc

Finish at Low