AD6620AS datasheet(6/44 Pages) AD

Part #	AD6620AS

Description	67 MSPS Digital Receive Signal Processor

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AD6620

–6–

REV. A

TIMING CHARACTERISTICS (C

LOAD = 40 pF All Outputs)

Test

AD6620AS

Parameter (Conditions)

Temp

Level

Min

Typ

Max

Unit

MICROPROCESSOR PORT, MODE = 0

MODE0 Input Timing Requirements:

tSC

Control

1 to CLK Setup Time

Full

IV

3.0

ns

tHC

Control1 to CLK Hold Time

Full

IV

5.0

ns

tHA

Address

2 to CLK Hold Time

Full

IV

3.0

ns

tZR

CS to Data Enabled Time

Full

IV

5.0

ns

tZD

CS to Data Disabled Time

Full

IV

5.0

ns

tSAM

CS to Address/Data Setup Time

Full

IV

0.0

ns

MODE0 Read Switching Characteristics:

tDD

CLK to Data Valid Time

Full

I

10.0

15.0

30.0

ns

tRDY

RD to RDY Time

Full

IV

4.0

19.5

ns

MODE0 Write Timing Requirements:

tSC

Control

1 to CLK Setup Time

Full

IV

3.0

ns

tHC

Control

1 to CLK Hold Time

Full

IV

5.0

ns

tHM

Micro Data

3 to CLK Hold Time

Full

IV

3.0

ns

tHA

Address

2 to CLK Hold Time

Full

IV

3.0

ns

tSAM

Address/Data Setup Time to

CS

Full

IV

0.0

ns

MODE0 Write Switching Characteristics:

tRDY

RD to RDY Time

Full

IV

4.0

19.5

ns

MICROPROCESSOR PORT, MODE = 1

MODE1 Input Timing Requirements:

tSC

Control

1 to CLK Setup Time

Full

IV

3.0

ns

tHC

Control

1 to CLK Hold Time

Full

IV

5.0

ns

tHA

Address2 to CLK Hold Time

Full

IV

3.0

ns

tZR

CS to Data Enabled Time

Full

IV

5.0

ns

tZD

CS to Data Disabled Time

Full

IV

5.0

ns

tSAM

Address/Data Setup Time to

CS

Full

IV

0.0

ns

MODE1 Read Switching Characteristics:

tDD

CLK to Data Valid Time

Full

I

10.0

30.0

ns

tDTACK

CLK to DTACK Time

Full

V

5.5

15.5

ns

MODE1 Write Timing Requirements:

tSC

Control

1 to CLK Setup Time

Full

IV

0.0

ns

tHC

Control

1 to CLK Hold Time

Full

IV

5.0

ns

tHM

Micro Data

3 to CLK Hold Time

Full

IV

6.5

ns

tHA

Address

2 to CLK Hold Time

Full

IV

3.0

ns

tSAM

Address/Data Setup Time to

CS

Full

IV

0.0

ns

MODE1 Write Switching Characteristic:

tDTACK

CLK to DTACK Time

Full

V

5.5

15.5

ns

NOTES

1Specification pertains to: R/W (

WR), DS (RD), CS.

2Specification pertains to: A[2:0].

3Specification pertains to: D[7:0].

Specifications subject to change without notice.

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