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BR93G46FVM-3ATR Datasheet(PDF) 5 Page - Rohm

Part # BR93G46FVM-3ATR
Description  Serial EEPROM series Standard EEPROM
Download  39 Pages
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Manufacturer  ROHM [Rohm]
Direct Link  http://www.rohm.com
Logo ROHM - Rohm

BR93G46FVM-3ATR Datasheet(HTML) 5 Page - Rohm

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Datasheet
Datasheet
BR93G46-3A
www.rohm.com
TSZ02201-09190G100140-1-2
18.FEB.2013 REV.001
© 2013 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
●Serial input / output timing
○Data is taken by DI sync with the rise of SK.
○At read operation, data is output from DO in sync with the rise of SK.
○The STATUS signal at write (READY / BUSY) is output after tCS from the fall of CS after write command input, at the area
DO where CS is high, and valid until the next command start bit is input. And, while CS is low, DO becomes High-Z.
○After completion of each mode execution, set CS low once for internal circuit reset, and execute the following operation
mode.
○1/fSK is the SK clock cycle, even if fSK is maximum, the SK clock cycle can’t be tSKH(Min.)+tSKL(Min.)
○For “Write cycle time tE/W”, please see Figure 36,37,39,40.
○For “CS low time tCS”, please see Figure 36,37,39,40.
●Block diagram
Figure 1. Sync data input / output timing
CS
SK
DO(READ)
DI
DO(WRITE)
tCSS
tSKH
tSKL
tCSH
tDIS
tD IH
tPD1
tPD0
t DF
STATUS VALID
tSV
1/ fSK
Figure 2. Block diagram
Command decode
Control
Clock generation
Power source voltage detection
Write
prohibition
High voltage occurrence
Command
register
Address
buffer
SK
DI
Dummy bit
DO
Data
register
R/W
amplifier
6bit
6bit
16bit
16bit
1,024 bit
EEPROM
CS
Address
decoder


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