BR93H56-2C

4/29

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19.DEC.2012 Rev.002

TSZ22111・15・001

© 2012 ROHM Co., Ltd. All rights reserved.

TSZ02201-0R1R0G100020-1-2

Datasheet

Datasheet

Serial Input / Output Timing

○Data is taken from DI, in sync with the rise of SK.

○At READ command, data is outputted from DO in sync with the rise of SK.

○After WRITE command input, the status signal of WRITE (READY / BUSY) can be monitored from DO by setting CS to “H”

But, if CS is set to

“L”, DO sets to High-Z state.

○To execute a series of commands, CS is set to “L” once after completion of each command for internal circuit reset.

Block Diagram

Figure 1 Serial Input / Output Timing Diagram

Figure 2

Block Diagram

Command decode

Control

Clock generation

Power source voltage detection

Write

prohibition

High voltage occurrence

Command

register

Address

buffer

SK

DI

Dummy bit

DO

Data

register

R/W

amplifier

16bit

16bit

2,048 bit

EEPROM

CS

Address

decoder

7bit

7bit

tCSS

CS

SK

tDF

tSKH

tSKL

tCSH

STATUS VALID

DI

tDIH

tDIS

tPD0

tPD1