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EP2AGX95EF29I5N Datasheet(PDF) 82 Page - Altera Corporation |
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EP2AGX95EF29I5N Datasheet(HTML) 82 Page - Altera Corporation |
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82 / 90 page  1–74 Chapter 1: Device Datasheet for Arria II Devices Glossary Arria II Device Handbook Volume 3: Device Datasheet and Addendum July 2012 Altera Corporation Glossary Table 1–68 lists the glossary for this chapter. Table 1–68. Glossary (Part 1 of 4) Letter Subject Definitions A, B, C, D Differential I/O Standards Receiver Input Waveforms Transmitter Output Waveforms E, F fHSCLK Left/Right PLL input clock frequency. fHSDR High-speed I/O block: Maximum/minimum LVDS data transfer rate (fHSDR = 1/TUI), non-DPA. fHSDRDPA High-speed I/O block: Maximum/minimum LVDS data transfer rate (fHSDRDPA = 1/TUI), DPA. Single-Ended Waveform Differential Waveform Positive Channel (p) = VIH Negative Channel (n) = VIL Ground VID VID VID p − n = 0 V VCM Single-Ended Waveform Differential Waveform Positive Channel (p) = VOH Negative Channel (n) = VOL Ground VOD VOD VOD p − n = 0 V VCM |
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