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EP2AGX95EF29I5N Datasheet(PDF) 84 Page - Altera Corporation |
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EP2AGX95EF29I5N Datasheet(HTML) 84 Page - Altera Corporation |
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84 / 90 page  1–76 Chapter 1: Device Datasheet for Arria II Devices Glossary Arria II Device Handbook Volume 3: Device Datasheet and Addendum July 2012 Altera Corporation S SW (sampling window) The period of time during which the data must be valid in order to capture it correctly. The setup and hold times determine the ideal strobe position within the sampling window: Timing Diagram Single-ended Voltage Referenced I/O Standard The JEDEC standard for SSTL and HSTL I/O standards define both the AC and DC input signal values. The AC values indicate the voltage levels at which the receiver must meet its timing specifications. The DC values indicate the voltage levels at which the final logic state of the receiver is unambiguously defined. After the receiver input has crossed the AC value, the receiver changes to the new logic state. The new logic state is then maintained as long as the input stays beyond the AC threshold. This approach is intended to provide predictable receiver timing in the presence of input waveform ringing: Single-Ended Voltage Referenced I/O Standard T tC High-speed receiver and transmitter input and output clock period. TCCS (channel-to- channel- skew) The timing difference between the fastest and slowest output edges, including tCO variation and clock skew, across channels driven by the same PLL. The clock is included in the TCCS measurement (refer to the Timing Diagram figure under S in this table). tDUTY High-speed I/O block: Duty cycle on the high-speed transmitter output clock. Timing Unit Interval (TUI) The timing budget allowed for skew, propagation delays, and data sampling window. (TUI = 1/(Receiver Input Clock Frequency Multiplication Factor) = tC/w) tFALL Signal high-to-low transition time (80-20%) tINCCJ Cycle-to-cycle jitter tolerance on the PLL clock input. tOUTPJ_IO Period jitter on the general purpose I/O driven by a PLL. tOUTPJ_DC Period jitter on the dedicated clock output driven by a PLL. tRISE Signal low-to-high transition time (20-80%). Table 1–68. Glossary (Part 3 of 4) Letter Subject Definitions Bit Time 0.5 x TCCS RSKM Sampling Window (SW) RSKM 0.5 x TCCS VIH(AC) VIH(DC) VREF VIL(DC) VIL(AC) VOH VOL VCCIO VSS |
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