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EP1SGX40 Datasheet(PDF) 2 Page - Altera Corporation

Part # EP1SGX40
Description  Enhanced Configuration (EPC) Devices Datasheet
Download  36 Pages
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Manufacturer  ALTERA [Altera Corporation]
Direct Link  http://www.altera.com
Logo ALTERA - Altera Corporation

EP1SGX40 Datasheet(HTML) 2 Page - Altera Corporation

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Functional Description
Enhanced Configuration (EPC) Devices Datasheet
January 2012
Altera Corporation
Pin selectable 2-ms or 100-ms power-on reset (POR) time
Configuration clock supports programmable input source and frequency synthesis
Multiple configuration clock sources supported (internal oscillator and
external clock input pin)
External clock source with frequencies up to 100 MHz
Internal oscillator defaults to 10 MHz and you can program the internal
oscillator for higher frequencies of 33, 50, and 66 MHz
Clock synthesis supported using user programmable divide counter
Available in the 100-pin plastic quad flat pack (PQFP) and the 88-pin Ultra
FineLine BGA (UFBGA) packages
Vertical migration between all devices supported in the 100-pin PQFP package
Supply voltage of 3.3 V (core and I/O)
Hardware compliant with IEEE Std. 1532 in-system programmability (ISP)
specification
Supports ISP using Jam Standard Test and Programming Language (STAPL)
Supports JTAG boundary scan
The nINIT_CONF pin allows private JTAG instruction to start FPGA configuration
Internal pull-up resistor on the nINIT_CONF pin always enabled
User programmable weak internal pull-up resistors on nCS and OE pins
Internal weak pull-up resistors on external flash interface address and control
lines, bus hold on data lines
Standby mode with reduced power consumption
f For more information about FPGA configuration schemes and advanced features,
refer to the configuration chapter in the appropriate device handbook.
Functional Description
The Altera EPC device is a single device with high speed and advanced configuration
solution for high-density FPGAs. The core of an EPC device is divided into two major
blocks—a configuration controller and a flash memory. The flash memory is used to
store configuration data for systems made up of one or more than one Altera FPGAs.
Unused portions of the flash memory can be used to store processor code or data that
can be accessed using the external flash interface after the FPGA configuration is
complete.


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