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EP2C8AT324I7N Datasheet(PDF) 15 Page - Altera Corporation

Part No. EP2C8AT324I7N
Description  Section I. Cyclone II Device Family Data Sheet
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Manufacturer  ALTERA [Altera Corporation]
Direct Link  http://www.altera.com
Logo ALTERA - Altera Corporation

EP2C8AT324I7N Datasheet(HTML) 15 Page - Altera Corporation

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Altera Corporation
2–3
February 2007
Cyclone II Device Handbook, Volume 1
Cyclone II Architecture
Figure 2–2 shows a Cyclone II LE.
Figure 2–2. Cyclone II LE
Each LE’s programmable register can be configured for D, T, JK, or SR
operation. Each register has data, clock, clock enable, and clear inputs.
Signals that use the global clock network, general-purpose I/O pins, or
any internal logic can drive the register’s clock and clear control signals.
Either general-purpose I/O pins or internal logic can drive the clock
enable. For combinational functions, the LUT output bypasses the
register and drives directly to the LE outputs.
Each LE has three outputs that drive the local, row, and column routing
resources. The LUT or register output can drive these three outputs
independently. Two LE outputs drive column or row and direct link
routing connections and one drives local interconnect resources, allowing
the LUT to drive one output while the register drives another output. This
feature, register packing, improves device utilization because the device
can use the register and the LUT for unrelated functions. When using
register packing, the LAB-wide synchronous load control signal is not
available. See “LAB Control Signals” on page 2–8 for more information.
labclk1
labclk2
labclr2
LAB Carry-In
Clock &
Clock Enable
Select
LAB Carry-Out
Look-Up
Table
(LUT)
Carry
Chain
Row, Column,
And Direct Link
Routing
Row, Column,
And Direct Link
Routing
Programmable
Register
CLRN
D
Q
ENA
Register Bypass
Packed
Register Select
Chip-Wide
Reset
(DEV_CLRn)
labclkena1
labclkena2
Synchronous
Load and
Clear Logic
LAB-Wide
Synchronous
Load
LAB-Wide
Synchronous
Clear
Asynchronous
Clear Logic
data1
data2
data3
data4
labclr1
Local Routing
Register Chain
Output
Register
Feedback
Register Chain
Routing From
Previous LE


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