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EP2C8AT324I7N Datasheet(PDF) 34 Page - Altera Corporation

Part No. EP2C8AT324I7N
Description  Section I. Cyclone II Device Family Data Sheet
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Manufacturer  ALTERA [Altera Corporation]
Direct Link  http://www.altera.com
Logo ALTERA - Altera Corporation

EP2C8AT324I7N Datasheet(HTML) 34 Page - Altera Corporation

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Altera Corporation
Cyclone II Device Handbook, Volume 1
February 2007
Global Clock Network & Phase-Locked Loops
Of the sources listed, only two clock pins, two PLL clock outputs, one
DPCLK
pin, and one internally-generated signal are chosen to drive into a
clock control block. Figure 2–13 shows a more detailed diagram of the
clock control block. Out of these six inputs, the two clock input pins and
two PLL outputs can be dynamic selected to feed a global clock network.
The clock control block supports static selection of DPCLK and the signal
from internal logic.
Figure 2–13. Clock Control Block
Notes to Figure 2–13:
(1)
The
CLKSWITCH signal can either be set through the configuration file or it can be dynamically set when using the
manual PLL switchover feature. The output of the multiplexer is the input reference clock (fIN) for the PLL.
(2)
The
CLKSELECT[1..0] signals are fed by internal logic and can be used to dynamically select the clock source for
the global clock network when the device is in user mode.
(3)
The static clock select signals are set in the configuration file and cannot be dynamically controlled when the device
is in user mode.
(4)
Internal logic can be used to enabled or disabled the global clock network in user mode.
CLKSWITCH (1)
Static Clock Select (3)
Static Clock
Select (3)
Internal Logic
Clock Control Block
DPCLK or
CDPCLK
CLKSELECT[1..0] (2)
CLKENA (4)
inclk1
inclk0
CLK[n + 3]
CLK[n + 2]
CLK[n + 1]
CLK[n]
fIN
C0
C1
C2
PLL
Global
Clock
Enable/
Disable
(3)


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