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EP2C8AT324I7N Datasheet(PDF) 39 Page - Altera Corporation

Part No. EP2C8AT324I7N
Description  Section I. Cyclone II Device Family Data Sheet
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Manufacturer  ALTERA [Altera Corporation]
Direct Link  http://www.altera.com
Logo ALTERA - Altera Corporation

EP2C8AT324I7N Datasheet(HTML) 39 Page - Altera Corporation

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Altera Corporation
2–27
February 2007
Cyclone II Device Handbook, Volume 1
Cyclone II Architecture
Figure 2–16 shows a block diagram of the Cyclone II PLL.
Figure 2–16. Cyclone II PLL
Note (1)
Notes to Figure 2–16:
(1)
This input can be single-ended or differential. If you are using a differential I/O standard, then two CLK pins are
used. LVDS input is supported via the secondary function of the dedicated CLK pins. For example, the CLK0 pin’s
secondary function is LVDSCLK1p and the CLK1 pin’s secondary function is LVDSCLK1n. If a differential I/O
standard is assigned to the PLL clock input pin, the corresponding CLK(n) pin is also completely used. The
Figure 2–16 shows the possible clock input connections (CLK0/CLK1) to PLL1.
(2)
This counter output is shared between a dedicated external clock output I/O and the global clock network.
f
For more information on Cyclone II PLLs, see the PLLs in the Cyclone II
Devices chapter in Volume 1 of the Cyclone II Device Handbook.
Embedded
Memory
The Cyclone II embedded memory consists of columns of M4K memory
blocks. The M4K memory blocks include input registers that synchronize
writes and output registers to pipeline designs and improve system
performance. The output registers can be bypassed, but input registers
cannot.
PFD
Loop
Filter
Lock Detect
& Filter
VCO
Charge
Pump
÷c0
÷c1
÷c2
÷m
÷n
Global
Clock
Global
Clock
Global
Clock
To I/O or
general routing
PLL<#>_OUT
Post-Scale
Counters
VCO Phase Selection
Selectable at Each
PLL Output Port
CLK1
CLK3
CLK2 (1)
CLK0 (1)
inclk0
inclk1
up
down
8
8
8
fVCO
fFB
fIN
Reference
Input Clock
fREF = fIN /n
(2)
Manual Clock
Switchover
Select Signal
÷k
(3)


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