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EP2C8AT324C8N Datasheet(PDF) 50 Page - Altera Corporation |
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EP2C8AT324C8N Datasheet(HTML) 50 Page - Altera Corporation |
50 / 168 page 2–38 Altera Corporation Cyclone II Device Handbook, Volume 1 February 2007 I/O Structure & Features Figure 2–20. Cyclone II IOE Structure Note to Figure 2–20: (1) There are two paths available for combinational or registered inputs to the logic array. Each path contains a unique programmable delay chain. The IOEs are located in I/O blocks around the periphery of the Cyclone II device. There are up to five IOEs per row I/O block and up to four IOEs per column I/O block (column I/O blocks span two columns). The row I/O blocks drive row, column (only C4 interconnects), or direct link interconnects. The column I/O blocks drive column interconnects. Figure 2–21 shows how a row I/O block connects to the logic array. Figure 2–22 shows how a column I/O block connects to the logic array. Output Register Output Input (1) OE Register OE Input Register Logic Array |
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