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EP2C8AT324C8N Datasheet(PDF) 51 Page - Altera Corporation

Part No. EP2C8AT324C8N
Description  Section I. Cyclone II Device Family Data Sheet
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Manufacturer  ALTERA [Altera Corporation]
Direct Link  http://www.altera.com
Logo ALTERA - Altera Corporation

EP2C8AT324C8N Datasheet(HTML) 51 Page - Altera Corporation

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Altera Corporation
2–39
February 2007
Cyclone II Device Handbook, Volume 1
Cyclone II Architecture
Figure 2–21. Row I/O Block Connection to the Interconnect
Notes to Figure 2–21:
(1)
The 35 data and control signals consist of five data out lines, io_dataout[4..0], five output enables,
io_coe[4..0]
, five input clock enables, io_cce_in[4..0], five output clock enables, io_cce_out[4..0],
five clocks, io_cclk[4..0], five asynchronous clear signals, io_caclr[4..0], and five synchronous clear
signals, io_csclr[4..0].
(2)
Each of the five IOEs in the row I/O block can have two io_datain (combinational or registered) inputs.
35
R4 & R24 Interconnects
C4 Interconnects
I/O Block Local
Interconnect
35 Data and
Control Signals
from Logic Array (1)
io_datain0[4..0]
io_datain1[4..0] (2)
io_clk[5..0]
Row I/O Block
Contains up to
Five IOEs
Direct Link
Interconnect
to Adjacent LAB
Direct Link
Interconnect
from Adjacent LAB
LAB Local
Interconnect
LAB
Row
I/O Block


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