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EP2C8AT324C8N Datasheet(PDF) 72 Page - Altera Corporation |
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EP2C8AT324C8N Datasheet(HTML) 72 Page - Altera Corporation |
72 / 168 page 2–60 Altera Corporation Cyclone II Device Handbook, Volume 1 February 2007 I/O Structure & Features standards (e.g., SSTL-2) independently. If an I/O bank does not use voltage-referenced standards, the VREF pins are available as user I/O pins. Each I/O bank can support multiple standards with the same VCCIO for input and output pins. For example, when VCCIO is 3.3-V, a bank can support LVTTL, LVCMOS, and 3.3-V PCI for inputs and outputs. Voltage-referenced standards can be supported in an I/O bank using any number of single-ended or differential standards as long as they use the same VREF and a compatible VCCIO value. MultiVolt I/O Interface The Cyclone II architecture supports the MultiVolt I/O interface feature, which allows Cyclone II devices in all packages to interface with systems of different supply voltages. Cyclone II devices have one set of VCC pins (VCCINT) that power the internal device logic array and input buffers that use the LVPECL, LVDS, HSTL, or SSTL I/O standards. Cyclone II devices also have four or eight sets of VCC pins (VCCIO) that power the I/O output drivers and input buffers that use the LVTTL, LVCMOS, or PCI I/O standards. The Cyclone II VCCINT pins must always be connected to a 1.2-V power supply. If the VCCINT level is 1.2 V, then input pins are 1.5-V, 1.8-V, 2.5-V, and 3.3-V tolerant. The VCCIO pins can be connected to either a 1.5-V, 1.8-V, 2.5-V, or 3.3-V power supply, depending on the output requirements. The output levels are compatible with systems of the same voltage as the power supply (i.e., when VCCIO pins are connected to a 1.5-V power supply, the output levels are compatible with 1.5-V systems). When VCCIO pins are connected to a 3.3-V power supply, the output high is 3.3-V and is compatible with 3.3-V systems. Table 2–20 summarizes Cyclone II MultiVolt I/O support. Table 2–20. Cyclone II MultiVolt I/O Support (Part 1 of 2) Note (1) VCCIO (V) Input Signal Output Signal 1.5 V 1.8 V 2.5 V 3.3 V 1.5 V 1.8 V 2.5 V 3.3 V 1.5 vv v (2) v (2) v 1.8 v (4) v v (2) v (2) v (3) v 2.5 vv v (5) v (5) v |
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