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EP2C8AT324C8N Datasheet(PDF) 97 Page - Altera Corporation

Part No. EP2C8AT324C8N
Description  Section I. Cyclone II Device Family Data Sheet
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Manufacturer  ALTERA [Altera Corporation]
Direct Link  http://www.altera.com
Logo ALTERA - Altera Corporation

EP2C8AT324C8N Datasheet(HTML) 97 Page - Altera Corporation

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Altera Corporation
5–7
February 2008
Cyclone II Device Handbook, Volume 1
DC Characteristics and Timing Specifications
Differential I/O Standards
The RSDS and mini-LVDS I/O standards are only supported on output
pins. The LVDS I/O standard is supported on both receiver input pins
and transmitter output pins.
1
For more information on how these differential I/O standards
are implemented, refer to the High-Speed Differential Interfaces in
Cyclone II Devices chapter of the Cyclone II Device Handbook.
Figure 5–1 shows the receiver input waveforms for all differential I/O
standards (LVDS, LVPECL, differential 1.5-V HSTL class I and II,
differential 1.8-V HSTL class I and II, differential SSTL-2 class I and II, and
differential SSTL-18 class I and II).
1.5-V HSTL class I
8
–8
0.4
VCCIO – 0.4
1.5V HSTL class II
16
–16
0.4
VCCIO – 0.4
Notes to Table 5–7:
(1)
The values in this table are based on the conditions listed in Tables 5–2 and 5–6.
(2)
This specification is supported across all the programmable drive settings available as shown in the Cyclone II
Architecture chapter of the Cyclone II Device Handbook.
Table 5–7. DC Characteristics of User I/O Pins Using Single-Ended Standards Notes (1), (2) (Part 2 of 2)
I/O Standard
Test Conditions
Voltage Thresholds
IOL (mA)
IOH (mA)
Maximum VOL (V)
Minimum VOH (V)


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