Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.NET

X  

Preview PDF Download HTML

EP2C8AT324C8N Datasheet(PDF) 99 Page - Altera Corporation

Part No. EP2C8AT324C8N
Description  Section I. Cyclone II Device Family Data Sheet
Download  168 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  ALTERA [Altera Corporation]
Direct Link  http://www.altera.com
Logo ALTERA - Altera Corporation

EP2C8AT324C8N Datasheet(HTML) 99 Page - Altera Corporation

Back Button EP2C8AT324C8N Datasheet HTML 95Page - Altera Corporation EP2C8AT324C8N Datasheet HTML 96Page - Altera Corporation EP2C8AT324C8N Datasheet HTML 97Page - Altera Corporation EP2C8AT324C8N Datasheet HTML 98Page - Altera Corporation EP2C8AT324C8N Datasheet HTML 99Page - Altera Corporation EP2C8AT324C8N Datasheet HTML 100Page - Altera Corporation EP2C8AT324C8N Datasheet HTML 101Page - Altera Corporation EP2C8AT324C8N Datasheet HTML 102Page - Altera Corporation EP2C8AT324C8N Datasheet HTML 103Page - Altera Corporation Next Button
Zoom Inzoom in Zoom Outzoom out
 99 / 168 page
background image
Altera Corporation
5–9
February 2008
Cyclone II Device Handbook, Volume 1
DC Characteristics and Timing Specifications
Table 5–8 shows the recommended operating conditions for user I/O
pins with differential I/O standards.
Table 5–8. Recommended Operating Conditions for User I/O Pins Using Differential Signal I/O Standards
I/O
Standard
VCCIO (V)
VID (V) (1)
VICM (V)
VIL (V)
VIH (V)
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Min
Max
Min
Max
LVDS
2.375
2.5
2.625
0.1
0.65
0.1
2.0
Mini-LVDS
(2)
2.375
2.5
2.625
————
RSDS (2)
2.375
2.5
2.625
————
LVPECL
(3) (6)
3.135
3.3
3.465
0.1
0.6
0.95
0
2.2
2.1
2.88
Differential
1.5-V HSTL
class I
and II (4)
1.425
1.5
1.575
0.2
VCCIO
+ 0.6
0.68
0.9
VREF
– 0.20
VREF
+ 0.20
Differential
1.8-V HSTL
class I
and II (4)
1.71
1.8
1.89
————
VREF
– 0.20
VREF
+ 0.20
Differential
SSTL-2
class I
and II (5)
2.375
2.5
2.625
0.36
VCCIO
+ 0.6
0.5 ×
VCCIO
– 0.2
0.5 ×
VCCIO
0.5 ×
VCCIO
+ 0.2
—VREF
– 0.35
VREF
+ 0.35
Differential
SSTL-18
class I
and II (5)
1.7
1.8
1.9
0.25
VCCIO
+ 0.6
0.5 ×
VCCIO
– 0.2
0.5 ×
VCCIO
0.5 ×
VCCIO
+ 0.2
—VREF
– 0.25
VREF
+ 0.25
Notes to Table 5–8:
(1)
Refer to the High-Speed Differential Interfaces in Cyclone II Devices chapter of the Cyclone II Device Handbook for
measurement conditions on VID.
(2)
The RSDS and mini-LVDS I/O standards are only supported on output pins.
(3)
The LVPECL I/O standard is only supported on clock input pins. This I/O standard is not supported on output
pins.
(4)
The differential 1.8-V and 1.5-V HSTL I/O standards are only supported on clock input pins and PLL output clock
pins.
(5)
The differential SSTL-18 and SSTL-2 I/O standards are only supported on clock input pins and PLL output clock
pins.
(6)
The LVPECL clock inputs are powered by VCCINT and support all VCCIO settings. However, it is recommended to
connect VCCIO to typical value of 3.3V.


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24  25  26  27  28  29  30  31  32  33  34  35  36  37  38  39  40  41  42  43  44  45  46  47  48  49  50  51  52  53  54  55  56  57  58  59  60  61  62  63  64  65  66  67  68  69  70  71  72  73  74  75  76  77  78  79  80  81  82  83  84  85  86  87  88  89  90  91  92  93  94  95  96  97  98  99  100   ...More


Datasheet Download

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEET.NET
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn