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SN65HVD102 Datasheet(PDF) 10 Page - Texas Instruments |
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SN65HVD102 Datasheet(HTML) 10 Page - Texas Instruments |
10 / 23 page Over-current caused by transient Wake-Up Pulse from Master Node Over-current caused by fault condition EN = H, TX = L EN = H, TX = H CQ RX WAKE CUR_OK CQ RX WAKE CUR_OK 80 s ± 5 s m m < 45 s m < 45 s m CQ RX WAKE CUR_OK CQ RX WAKE CUR_OK 80 s ± 5 s m m t WAKE P t WAKE P > 250 s m CQ RX WAKE CUR_OK CQ RX WAKE CUR_OK > 250 s m t SC P t SC P SN65HVD101 SN65HVD102 SLLSE84A – MAY 2011 – REVISED MARCH 2013 www.ti.com Figure 7. Over-Current and Wake Conditions Current Limit Indication, Short Circuit Current Detection If the output current at CQ remains at the internally set current limit IO(LIM) for a duration longer than a wake-up pulse (longer than 80 usec) the CUR_OK pin will be driven to a logic LOW state. The CUR_OK pin will return to the high-impedance (inactive) state when the CQ pin is no longer in a current limit condition. The state diagram shown in Figure 8 illustrates the various states and under what conditions the device transitions from one state to another. 10 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: SN65HVD101 SN65HVD102 |
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