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SN65HVD101 Datasheet(PDF) 4 Page - Texas Instruments |
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SN65HVD101 Datasheet(HTML) 4 Page - Texas Instruments |
4 / 23 page SN65HVD101 SN65HVD102 SLLSE84A – MAY 2011 – REVISED MARCH 2013 www.ti.com Table 5. Temperature Indicator Function Internal Temperature Overtemp (Internal) TEMP_OK Comment T < TWARN not overtemp Z Normal operation TWARN < T↑ < TSD not overtemp L Temperature warning TSD < T overtemp disable L Overtemp disable TWARN < T↓ < TRE not overtemp L Temperature recovery Table 6. Power Supply Indicator Function VL+ VCC PWR_OK Comment VL+ < VPG1 VPOR2 < VCC < VPG2 L Both supplies too low VPG1 < VL+ VPOR2 < VCC < VPG2 L VCC too low VL+ < VPG1 VPG2 < VCC L VL+ too low VPG1 < VL+ VPG2 < VCC Z Both supplies correct THERMAL INFORMATION SN65HVD10x THERMAL METRIC(1) RGB PACKAGE UNITS 20 PINS θJA Junction-to-ambient thermal resistance 33.8 θJCtop Junction-to-case (top) thermal resistance 36.6 θJB Junction-to-board thermal resistance 10.3 °C/W ψJT Junction-to-top characterization parameter 0.4 ψJB Junction-to-board characterization parameter 10.3 θJCbot Junction-to-case (bottom) thermal resistance 2.3 TSTG Storage temperature 65 to 150 °C (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) VALUE UNIT MIN MAX Line voltage – steady state –40 +40(2) (3) V L+, CQ Line Voltage – transient, pulse width <100us +50 V VCC Supply voltage –0.3 6 V V TX, EN, VCC_SET, ILIMADJ, Input voltage –0.3 6 V RX, CUR_OK, WAKE, Output voltage –0.3 6 V PWR_OK RX, CUR_OK, WAKE, IO Output current TBD mA PWR_OK Tstg Storage temperature –65 150 °C TJ Die temperature 180 °C ESD HBM (all pins) 2 kV (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltages are with reference to the GND pin, unless otherwise specified. (3) GND pin and L- line should be at the same DC potential 4 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: SN65HVD101 SN65HVD102 |
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