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BD49E57 Datasheet(PDF) 10 Page - Rohm |
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BD49E57 Datasheet(HTML) 10 Page - Rohm |
10 / 17 page Datasheet 10/14 BD48Exxx-M series BD49Exxx-M series TSZ02201-0R7R0G300070-1-2 © 2013 ROHM Co., Ltd. All rights reserved. 22.May.2013.Rev.003 www.rohm.com TSZ22111 ・ 15 ・ 001 ● Application Information Explanation of Operation For both the open drain type (Fig.12) and the CMOS output type (Fig.13), the detection and release voltages are used as threshold voltages. When the voltage applied to the VDD pins reaches the applicable threshold voltage, the VOUT terminal voltage switches from either “High” to “Low” or from “Low” to “High”. Please refer to the Timing Waveform and Electrical Characteristics for information on hysteresis. Because the BD48Exxx-M series uses an open drain output type, it is necessary to connect a pull-up resistor to VDD or another power supply if needed [The output “High” voltage (VOUT) in this case becomes VDD or the voltage of the other power supply]. Fig.12 (BD48Exxx-M series Internal Block Diagram) Fig.13 (BD49Exxx-M series Internal Block Diagram) Reference Data Examples of Leading (tPLH) and Falling (tPHL) Output Part Number tPLH (µs) tPHL (µs) BD48E45G-M 39.5 87.8 BD49E45G-M 32.4 52.4 VDD=4.3V 5.1V VDD=5.1V 4.3V *This data is for reference only. The figures will vary with the application, so please confirm actual operating conditions before use. Timing Waveform Example: the following shows the relationship between the input voltages VDD and the output voltage VOUT when the input power supply voltage VDD is made to sweep up and sweep down (the circuits are those in Fig.12 and 13). 1 When the power supply is turned on, the output is unstable from after over the operating limit voltage (VOPL) until tPHL. Therefore it is possible that the reset signal is not valid when the rise time of VDD is faster than tPHL. 2 When VDD is greater than VOPL, but less than the reset release voltage (VDET + ∆VDET), the output voltages will switch to Low. 3 If VDD exceeds the reset release voltage (VDET + ∆VDET), then, VOUT switches from L to H. 4 If VDD drops below the detection voltage (VDET) when the power supply is powered down or when there is a power supply fluctuation, VOUT switches to L (with a delay of tPHL). 5 The potential difference between the detection voltage and the release voltage is known as the hysteresis width (∆VDET). The system is designed such that the output does not toggle with power supply fluctuations within this hysteresis width, preventing the malfunctions due to noise. VDD VDET+ Δ VDET VDET VOPL 0V tPHL ① ② VOUT tPLH tPHL tPLH ③ ④ VOL VOH ⑤ Fig.14 Timing Waveform Vref R1 R2 VDD GND Q1 VOUT R3 RL Vref R1 R2 R3 Q2 Q1 VDD VOUT GND |
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