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ISL62773IRZ Datasheet(PDF) 7 Page - Intersil Corporation |
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ISL62773IRZ Datasheet(HTML) 7 Page - Intersil Corporation |
7 / 37 page ISL62773 7 March 7, 2012 FN8263.0 Pin Configuration ISL62773 (48 LD QFN) TOP VIEW 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 BOOTX VIN BOOT2 UGATE2 PHASE2 LGATE2 VDDP VDD PWM_Y LGATE1 PHASE1 UGATE1 ISEN2_NB NTC_NB IMON_NB SVC VR_HOT_L SVD VDDIO SVT ENABLE PWROK IMON NTC GND PAD (BOTTOM) Pin Descriptions PIN NUMBER SYMBOL DESCRIPTION 1 ISEN2_NB Individual current sensing for Channel 2 of the Northbridge VR. When ISEN2_NB is pulled to +5V, the controller will disable Channel 2 and the Northbridge VR will run single-phase. 2 NTC_NB Thermistor input to VR_HOT_L circuit to monitor Northbridge VR temperature. 3 IMON_NB Northbridge output current monitor. A current proportional to the Northbridge VR output current is sourced from this pin. 4SVC Serial VID clock input from the CPU processor master device. 5 VR_HOT_L Thermal indicator signal to AMD CPU. Thermal overload open drain output indicator active LOW. 6 SVD Serial VID data bi-directional signal from the CPU processor master device to the VR. 7 VDDIO VDDIO is the processor memory interface power rail and this pin serves as the reference to the controller IC for this processor I/O signal level. 8 SVT Serial VID Telemetry (SVT) data line input to the CPU from the controller IC. Telemetry and VID-on-the-fly complete signal provided on from this pin. 9 ENABLE Enable input. A high level logic on this pin enables both VRs. 10 PWROK System power good input. When this pin is high, the SVI 2 interface is active and the I2C protocol is running. While this pin is low, the SVC and SVD input states determine the pre-PWROK metal VID. This pin must be low prior to the ISL62773 PGOOD output going high per the AMD SVI 2.0 Controller Guidelines. 11 IMON Core output current monitor. A current proportional to the Core VR output current is sourced from this pin. 12 NTC Thermistor input to VR_HOT_L circuit to monitor Core VR temperature. 13 ISEN3 ISEN3 is the individual current sensing for Channel 3. When ISEN3 is pulled to +5V, the controller disables Channel 3, and the Core VR runs in two-phase mode. |
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